dram_rot_gen.hh revision 12396:3d04ea44fafb
1/* 2 * Copyright (c) 2012-2013, 2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed here under. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Thomas Grass 38 * Andreas Hansson 39 * Sascha Bischoff 40 * Neha Agarwal 41 */ 42 43/** 44 * @file 45 * Declaration of DRAM rotation generator that rotates 46 * through each rank. 47 */ 48 49#ifndef __CPU_TRAFFIC_GEN_DRAM_ROT_GEN_HH__ 50#define __CPU_TRAFFIC_GEN_DRAM_ROT_GEN_HH__ 51 52#include "base/bitfield.hh" 53#include "base/intmath.hh" 54#include "dram_gen.hh" 55#include "mem/packet.hh" 56#include "proto/protoio.hh" 57 58class DramRotGen : public DramGen 59{ 60 61 public: 62 63 /** 64 * Create a DRAM address sequence generator. 65 * This sequence generator will rotate through: 66 * 1) Banks per rank 67 * 2) Command type (if applicable) 68 * 3) Ranks per channel 69 * 70 * @param _name Name to use for status and debug 71 * @param master_id MasterID set on each request 72 * @param _duration duration of this state before transitioning 73 * @param start_addr Start address 74 * @param end_addr End address 75 * @param _blocksize Size used for transactions injected 76 * @param min_period Lower limit of random inter-transaction time 77 * @param max_period Upper limit of random inter-transaction time 78 * @param read_percent Percent of transactions that are reads 79 * @param data_limit Upper limit on how much data to read/write 80 * @param num_seq_pkts Number of packets per stride, each of _blocksize 81 * @param page_size Page size (bytes) used in the DRAM 82 * @param nbr_of_banks_DRAM Total number of banks in DRAM 83 * @param nbr_of_banks_util Number of banks to utilized, 84 * for N banks, we will use banks: 0->(N-1) 85 * @param nbr_of_ranks Number of ranks utilized, 86 * @param addr_mapping Address mapping to be used, 87 * 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo 88 * assumes single channel system 89 */ 90 DramRotGen(const std::string& _name, MasterID master_id, Tick _duration, 91 Addr start_addr, Addr end_addr, Addr _blocksize, 92 Tick min_period, Tick max_period, 93 uint8_t read_percent, Addr data_limit, 94 unsigned int num_seq_pkts, unsigned int page_size, 95 unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, 96 unsigned int addr_mapping, 97 unsigned int nbr_of_ranks, 98 unsigned int max_seq_count_per_rank) 99 : DramGen(_name, master_id, _duration, start_addr, end_addr, 100 _blocksize, min_period, max_period, read_percent, data_limit, 101 num_seq_pkts, page_size, nbr_of_banks_DRAM, 102 nbr_of_banks_util, addr_mapping, 103 nbr_of_ranks), 104 maxSeqCountPerRank(max_seq_count_per_rank), 105 nextSeqCount(0) 106 { 107 // Rotating traffic generation can only support a read 108 // percentage of 0, 50, or 100 109 if (readPercent != 50 && readPercent != 100 && readPercent != 0) { 110 fatal("%s: Unsupported read percentage for DramRotGen: %d", 111 _name, readPercent); 112 } 113 } 114 115 PacketPtr getNextPacket(); 116 117 private: 118 /** Number of command series issued before the rank is 119 changed. Should rotate to the next rank after rorating 120 throughall the banks for each specified command type */ 121 const unsigned int maxSeqCountPerRank; 122 123 /** Next packet series count used to set rank and bank, 124 and update isRead Incremented at the start of a new 125 packet series */ 126 unsigned int nextSeqCount; 127}; 128 129#endif 130