base_gen.hh revision 12844:c934a1338314
12SN/A/* 21762SN/A * Copyright (c) 2012-2013, 2017-2018 ARM Limited 32SN/A * All rights reserved 42SN/A * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed here under. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Redistribution and use in source and binary forms, with or without 152SN/A * modification, are permitted provided that the following conditions are 162SN/A * met: redistributions of source code must retain the above copyright 172SN/A * notice, this list of conditions and the following disclaimer; 182SN/A * redistributions in binary form must reproduce the above copyright 192SN/A * notice, this list of conditions and the following disclaimer in the 202SN/A * documentation and/or other materials provided with the distribution; 212SN/A * neither the name of the copyright holders nor the names of its 222SN/A * contributors may be used to endorse or promote products derived from 232SN/A * this software without specific prior written permission. 242SN/A * 252SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282665Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292665Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302665Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312665Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362SN/A * 3756SN/A * Authors: Thomas Grass 381717SN/A * Andreas Hansson 392518SN/A * Sascha Bischoff 4056SN/A * Neha Agarwal 412518SN/A */ 422518SN/A 432SN/A/** 442SN/A * @file 452SN/A * Declaration of the base generator class for all generators. 462SN/A */ 472SN/A 482SN/A#ifndef __CPU_TRAFFIC_GEN_BASE_GEN_HH__ 492SN/A#define __CPU_TRAFFIC_GEN_BASE_GEN_HH__ 502SN/A 512SN/A#include "base/bitfield.hh" 522SN/A#include "base/intmath.hh" 532SN/A#include "mem/packet.hh" 542SN/A 552SN/Aclass BaseTrafficGen; 561904SN/A 571968SN/A/** 581968SN/A * Base class for all generators, with the shared functionality and 591968SN/A * virtual functions for entering, executing and leaving the 601968SN/A * generator. 611968SN/A */ 621968SN/Aclass BaseGen 631967SN/A{ 641967SN/A 651967SN/A protected: 661967SN/A 671967SN/A /** Name to use for status and debug printing */ 681967SN/A const std::string _name; 691967SN/A 701967SN/A /** The MasterID used for generating requests */ 711967SN/A const MasterID masterID; 721967SN/A 731904SN/A /** 741904SN/A * Generate a new request and associated packet 751904SN/A * 761904SN/A * @param addr Physical address to use 77452SN/A * @param size Size of the request 781904SN/A * @param cmd Memory command to send 792SN/A * @param flags Optional request flags 801904SN/A */ 811904SN/A PacketPtr getPacket(Addr addr, unsigned size, const MemCmd& cmd, 822SN/A Request::FlagsType flags = 0); 831904SN/A 841904SN/A public: 852SN/A 862SN/A /** Time to spend in this state */ 871904SN/A const Tick duration; 881904SN/A 891904SN/A /** 901904SN/A * Create a base generator. 911904SN/A * 921904SN/A * @param obj simobject owning the generator 931904SN/A * @param master_id MasterID set on each request 941904SN/A * @param _duration duration of this state before transitioning 951904SN/A */ 961904SN/A BaseGen(SimObject &obj, MasterID master_id, Tick _duration); 971904SN/A 98452SN/A virtual ~BaseGen() { } 991904SN/A 1001904SN/A /** 1011904SN/A * Get the name, useful for DPRINTFs. 1022SN/A * 1032SN/A * @return the given name 1041904SN/A */ 1051904SN/A std::string name() const { return _name; } 1061904SN/A 1071904SN/A /** 1081904SN/A * Enter this generator state. 1091904SN/A */ 1102SN/A virtual void enter() = 0; 1111904SN/A 1122SN/A /** 1132SN/A * Get the next generated packet. 1141904SN/A * 1152SN/A * @return A packet to be sent at the current tick 1161904SN/A */ 1171904SN/A virtual PacketPtr getNextPacket() = 0; 1181904SN/A 1191904SN/A /** 1201904SN/A * Exit this generator state. By default do nothing. 1211904SN/A */ 1221904SN/A virtual void exit() { }; 1231904SN/A 1241904SN/A /** 1251904SN/A * Determine the tick when the next packet is available. MaxTick 1261904SN/A * means that there will not be any further packets in the current 1271904SN/A * activation cycle of the generator. 1281904SN/A * 1291904SN/A * @param elastic should the injection respond to flow control or not 1301904SN/A * @param delay time the previous packet spent waiting 1311904SN/A * @return next tick when a packet is available 1321904SN/A */ 1331904SN/A virtual Tick nextPacketTick(bool elastic, Tick delay) const = 0; 1341904SN/A 1351904SN/A}; 1362525SN/A 1371904SN/Aclass StochasticGen : public BaseGen 1382525SN/A{ 1392525SN/A public: 1402525SN/A StochasticGen(SimObject &obj, 1411904SN/A MasterID master_id, Tick _duration, 1421904SN/A Addr start_addr, Addr end_addr, 1431904SN/A Addr _blocksize, Addr cacheline_size, 1441904SN/A Tick min_period, Tick max_period, 1451904SN/A uint8_t read_percent, Addr data_limit); 1461904SN/A 1471904SN/A protected: 1481904SN/A /** Start of address range */ 1491967SN/A const Addr startAddr; 1501967SN/A 1511967SN/A /** End of address range */ 1521967SN/A const Addr endAddr; 1531967SN/A 1542SN/A /** Blocksize and address increment */ 1552SN/A const Addr blocksize; 1562SN/A 1572SN/A /** Cache line size in the simulated system */ 1582SN/A const Addr cacheLineSize; 1591967SN/A 1602SN/A /** Request generation period */ 1612SN/A const Tick minPeriod; 1622SN/A const Tick maxPeriod; 1632SN/A 1642SN/A /** 1652SN/A * Percent of generated transactions that should be reads 1662SN/A */ 1672SN/A const uint8_t readPercent; 1682SN/A 1692SN/A /** Maximum amount of data to manipulate */ 1702SN/A const Addr dataLimit; 1712SN/A}; 1722SN/A 1732SN/A#endif 1742SN/A