base.hh revision 12918 
1/*
2 * Copyright (c) 2012-2013, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grass
38 *          Andreas Hansson
39 *          Sascha Bischoff
40 */
41
42#ifndef __CPU_TRAFFIC_GEN_BASE_HH__
43#define __CPU_TRAFFIC_GEN_BASE_HH__
44
45#include <memory>
46#include <tuple>
47
48#include "base/statistics.hh"
49#include "mem/mem_object.hh"
50#include "mem/qport.hh"
51
52class BaseGen;
53class System;
54struct BaseTrafficGenParams;
55
56/**
57 * The traffic generator is a master module that generates stimuli for
58 * the memory system, based on a collection of simple generator
59 * behaviours that are either probabilistic or based on traces. It can
60 * be used stand alone for creating test cases for interconnect and
61 * memory controllers, or function as a black box replacement for
62 * system components that are not yet modelled in detail, e.g. a video
63 * engine or baseband subsystem.
64 */
65class BaseTrafficGen : public MemObject
66{
67    friend class BaseGen;
68
69  protected: // Params
70    /**
71     * The system used to determine which mode we are currently operating
72     * in.
73     */
74    System *const system;
75
76    /**
77     * Determine whether to add elasticity in the request injection,
78     * thus responding to backpressure by slowing things down.
79     */
80    const bool elasticReq;
81
82    /**
83     * Time to tolerate waiting for retries (not making progress),
84     * until we declare things broken.
85     */
86    const Tick progressCheck;
87
88  private:
89    /**
90     * Receive a retry from the neighbouring port and attempt to
91     * resend the waiting packet.
92     */
93    void recvReqRetry();
94
95    /** Transition to the next generator */
96    void transition();
97
98    /**
99     * Schedule the update event based on nextPacketTick and
100     * nextTransitionTick.
101     */
102    void scheduleUpdate();
103
104    /**
105     * Method to inform the user we have made no progress.
106     */
107    void noProgress();
108
109    /**
110     * Event to keep track of our progress, or lack thereof.
111     */
112    EventFunctionWrapper noProgressEvent;
113
114    /** Time of next transition */
115    Tick nextTransitionTick;
116
117    /** Time of the next packet. */
118    Tick nextPacketTick;
119
120
121    /** Master port specialisation for the traffic generator */
122    class TrafficGenPort : public MasterPort
123    {
124      public:
125
126        TrafficGenPort(const std::string& name, BaseTrafficGen& traffic_gen)
127            : MasterPort(name, &traffic_gen), trafficGen(traffic_gen)
128        { }
129
130      protected:
131
132        void recvReqRetry() { trafficGen.recvReqRetry(); }
133
134        bool recvTimingResp(PacketPtr pkt);
135
136        void recvTimingSnoopReq(PacketPtr pkt) { }
137
138        void recvFunctionalSnoop(PacketPtr pkt) { }
139
140        Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
141
142      private:
143
144        BaseTrafficGen& trafficGen;
145
146    };
147
148    /**
149     * Schedules event for next update and generates a new packet or
150     * requests a new generatoir depending on the current time.
151     */
152    void update();
153
154    /** The instance of master port used by the traffic generator. */
155    TrafficGenPort port;
156
157    /** Packet waiting to be sent. */
158    PacketPtr retryPkt;
159
160    /** Tick when the stalled packet was meant to be sent. */
161    Tick retryPktTick;
162
163    /** Event for scheduling updates */
164    EventFunctionWrapper updateEvent;
165
166    /** Count the number of dropped requests. */
167    Stats::Scalar numSuppressed;
168
169  private: // Stats
170    /** Count the number of generated packets. */
171    Stats::Scalar numPackets;
172
173    /** Count the number of retries. */
174    Stats::Scalar numRetries;
175
176    /** Count the time incurred from back-pressure. */
177    Stats::Scalar retryTicks;
178
179  public:
180    BaseTrafficGen(const BaseTrafficGenParams* p);
181
182    ~BaseTrafficGen() {}
183
184    BaseMasterPort& getMasterPort(const std::string &if_name,
185                                  PortID idx = InvalidPortID) override;
186
187    void init() override;
188
189    DrainState drain() override;
190
191    void serialize(CheckpointOut &cp) const override;
192    void unserialize(CheckpointIn &cp) override;
193
194    /** Register statistics */
195    void regStats() override;
196
197  public: // Generator factory methods
198    std::shared_ptr<BaseGen> createIdle(Tick duration);
199    std::shared_ptr<BaseGen> createExit(Tick duration);
200
201    std::shared_ptr<BaseGen> createLinear(
202        Tick duration,
203        Addr start_addr, Addr end_addr, Addr blocksize,
204        Tick min_period, Tick max_period,
205        uint8_t read_percent, Addr data_limit);
206
207    std::shared_ptr<BaseGen> createRandom(
208        Tick duration,
209        Addr start_addr, Addr end_addr, Addr blocksize,
210        Tick min_period, Tick max_period,
211        uint8_t read_percent, Addr data_limit);
212
213    std::shared_ptr<BaseGen> createDram(
214        Tick duration,
215        Addr start_addr, Addr end_addr, Addr blocksize,
216        Tick min_period, Tick max_period,
217        uint8_t read_percent, Addr data_limit,
218        unsigned int num_seq_pkts, unsigned int page_size,
219        unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
220        unsigned int addr_mapping,
221        unsigned int nbr_of_ranks);
222
223    std::shared_ptr<BaseGen> createDramRot(
224        Tick duration,
225        Addr start_addr, Addr end_addr, Addr blocksize,
226        Tick min_period, Tick max_period,
227        uint8_t read_percent, Addr data_limit,
228        unsigned int num_seq_pkts, unsigned int page_size,
229        unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
230        unsigned int addr_mapping,
231        unsigned int nbr_of_ranks,
232        unsigned int max_seq_count_per_rank);
233
234    std::shared_ptr<BaseGen> createTrace(
235        Tick duration,
236        const std::string& trace_file, Addr addr_offset);
237
238  protected:
239    void start();
240
241    virtual std::shared_ptr<BaseGen> nextGenerator() = 0;
242
243    /**
244     * MasterID used in generated requests.
245     */
246    const MasterID masterID;
247
248    /** Currently active generator */
249    std::shared_ptr<BaseGen> activeGenerator;
250};
251
252#endif //__CPU_TRAFFIC_GEN_BASE_HH__
253