base.hh revision 12810 
1/*
2 * Copyright (c) 2012-2013, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grass
38 *          Andreas Hansson
39 *          Sascha Bischoff
40 */
41
42#ifndef __CPU_TRAFFIC_GEN_BASE_HH__
43#define __CPU_TRAFFIC_GEN_BASE_HH__
44
45#include <memory>
46#include <tuple>
47
48#include "base/statistics.hh"
49#include "mem/mem_object.hh"
50#include "mem/qport.hh"
51
52class BaseGen;
53class System;
54struct BaseTrafficGenParams;
55
56/**
57 * The traffic generator is a master module that generates stimuli for
58 * the memory system, based on a collection of simple generator
59 * behaviours that are either probabilistic or based on traces. It can
60 * be used stand alone for creating test cases for interconnect and
61 * memory controllers, or function as a black box replacement for
62 * system components that are not yet modelled in detail, e.g. a video
63 * engine or baseband subsystem.
64 */
65class BaseTrafficGen : public MemObject
66{
67  protected: // Params
68    /**
69     * The system used to determine which mode we are currently operating
70     * in.
71     */
72    System *const system;
73
74    /**
75     * Determine whether to add elasticity in the request injection,
76     * thus responding to backpressure by slowing things down.
77     */
78    const bool elasticReq;
79
80    /**
81     * Time to tolerate waiting for retries (not making progress),
82     * until we declare things broken.
83     */
84    const Tick progressCheck;
85
86  private:
87    /**
88     * Receive a retry from the neighbouring port and attempt to
89     * resend the waiting packet.
90     */
91    void recvReqRetry();
92
93    /** Transition to the next generator */
94    void transition();
95
96    /**
97     * Schedule the update event based on nextPacketTick and
98     * nextTransitionTick.
99     */
100    void scheduleUpdate();
101
102    /**
103     * Method to inform the user we have made no progress.
104     */
105    void noProgress();
106
107    /**
108     * Event to keep track of our progress, or lack thereof.
109     */
110    EventFunctionWrapper noProgressEvent;
111
112    /** Time of next transition */
113    Tick nextTransitionTick;
114
115    /** Time of the next packet. */
116    Tick nextPacketTick;
117
118
119    /** Master port specialisation for the traffic generator */
120    class TrafficGenPort : public MasterPort
121    {
122      public:
123
124        TrafficGenPort(const std::string& name, BaseTrafficGen& traffic_gen)
125            : MasterPort(name, &traffic_gen), trafficGen(traffic_gen)
126        { }
127
128      protected:
129
130        void recvReqRetry() { trafficGen.recvReqRetry(); }
131
132        bool recvTimingResp(PacketPtr pkt);
133
134        void recvTimingSnoopReq(PacketPtr pkt) { }
135
136        void recvFunctionalSnoop(PacketPtr pkt) { }
137
138        Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
139
140      private:
141
142        BaseTrafficGen& trafficGen;
143
144    };
145
146    /**
147     * Schedules event for next update and generates a new packet or
148     * requests a new generatoir depending on the current time.
149     */
150    void update();
151
152    /** The instance of master port used by the traffic generator. */
153    TrafficGenPort port;
154
155    /** Packet waiting to be sent. */
156    PacketPtr retryPkt;
157
158    /** Tick when the stalled packet was meant to be sent. */
159    Tick retryPktTick;
160
161    /** Event for scheduling updates */
162    EventFunctionWrapper updateEvent;
163
164    uint64_t numSuppressed;
165
166  private: // Stats
167    /** Count the number of generated packets. */
168    Stats::Scalar numPackets;
169
170    /** Count the number of retries. */
171    Stats::Scalar numRetries;
172
173    /** Count the time incurred from back-pressure. */
174    Stats::Scalar retryTicks;
175
176  public:
177    BaseTrafficGen(const BaseTrafficGenParams* p);
178
179    ~BaseTrafficGen() {}
180
181    BaseMasterPort& getMasterPort(const std::string &if_name,
182                                  PortID idx = InvalidPortID) override;
183
184    void init() override;
185
186    DrainState drain() override;
187
188    void serialize(CheckpointOut &cp) const override;
189    void unserialize(CheckpointIn &cp) override;
190
191    /** Register statistics */
192    void regStats() override;
193
194  protected:
195    void start();
196
197    virtual std::shared_ptr<BaseGen> nextGenerator() = 0;
198
199    /**
200     * MasterID used in generated requests.
201     */
202    const MasterID masterID;
203
204    /** Currently active generator */
205    std::shared_ptr<BaseGen> activeGenerator;
206};
207
208#endif //__CPU_TRAFFIC_GEN_BASE_HH__
209