BaseTrafficGen.py revision 14053
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You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Thomas Grass 37# Andreas Hansson 38# Sascha Bischoff 39 40from m5.params import * 41from m5.proxy import * 42from m5.objects.ClockedObject import ClockedObject 43 44# Types of Stream Generators. 45# Those are orthogonal to the other generators in the TrafficGen 46# and are meant to initialize the stream and substream IDs for 47# every memory request, regardless of how the packet has been 48# generated (Random, Linear, Trace etc) 49class StreamGenType(Enum): vals = [ 'none', 'fixed', 'random' ] 50 51# The traffic generator is a master module that generates stimuli for 52# the memory system, based on a collection of simple behaviours that 53# are either probabilistic or based on traces. It can be used stand 54# alone for creating test cases for interconnect and memory 55# controllers, or function as a black-box replacement for system 56# components that are not yet modelled in detail, e.g. a video engine 57# or baseband subsystem in an SoC. 58class BaseTrafficGen(ClockedObject): 59 type = 'BaseTrafficGen' 60 abstract = True 61 cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh" 62 63 # Port used for sending requests and receiving responses 64 port = MasterPort("Master port") 65 66 # System used to determine the mode of the memory system 67 system = Param.System(Parent.any, "System this generator is part of") 68 69 # Should requests respond to back-pressure or not, if true, the 70 # rate of the traffic generator will be slowed down if requests 71 # are not immediately accepted 72 elastic_req = Param.Bool(False, 73 "Slow down requests in case of backpressure") 74 75 # Let the user know if we have waited for a retry and not made any 76 # progress for a long period of time. The default value is 77 # somewhat arbitrary and may well have to be tuned. 78 progress_check = Param.Latency('1ms', "Time before exiting " \ 79 "due to lack of progress") 80 81 # Generator type used for applying Stream and/or Substream IDs to requests 82 stream_gen = Param.StreamGenType('none', 83 "Generator for adding Stream and/or Substream ID's to requests") 84 85 # Sources for Stream/Substream IDs to apply to requests 86 sids = VectorParam.Unsigned([], "StreamIDs to use") 87 ssids = VectorParam.Unsigned([], "SubstreamIDs to use") 88 89 # These additional parameters allow TrafficGen to be used with scripts 90 # that expect a BaseCPU 91 cpu_id = Param.Int(-1, "CPU identifier") 92 socket_id = Param.Unsigned(0, "Physical Socket identifier") 93 numThreads = Param.Unsigned(1, "number of HW thread contexts") 94 95 @classmethod 96 def memory_mode(cls): 97 return 'timing' 98 99 @classmethod 100 def require_caches(cls): 101 return False 102 103 def createThreads(self): 104 pass 105 106 def createInterruptController(self): 107 pass 108 109 def connectCachedPorts(self, bus): 110 if hasattr(self, '_cached_ports') and (len(self._cached_ports) > 0): 111 for p in self._cached_ports: 112 exec('self.%s = bus.slave' % p) 113 else: 114 self.port = bus.slave 115 116 def connectAllPorts(self, cached_bus, uncached_bus = None): 117 self.connectCachedPorts(cached_bus) 118 119 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 120 self.dcache = dc 121 self.port = dc.cpu_side 122 self._cached_ports = ['dcache.mem_side'] 123 self._uncached_ports = [] 124