RubyTester.hh revision 9031
16899SN/A/* 26899SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 36899SN/A * Copyright (c) 2009 Advanced Micro Devices, Inc. 46899SN/A * All rights reserved. 56899SN/A * 66899SN/A * Redistribution and use in source and binary forms, with or without 76899SN/A * modification, are permitted provided that the following conditions are 86899SN/A * met: redistributions of source code must retain the above copyright 96899SN/A * notice, this list of conditions and the following disclaimer; 106899SN/A * redistributions in binary form must reproduce the above copyright 116899SN/A * notice, this list of conditions and the following disclaimer in the 126899SN/A * documentation and/or other materials provided with the distribution; 136899SN/A * neither the name of the copyright holders nor the names of its 146899SN/A * contributors may be used to endorse or promote products derived from 156899SN/A * this software without specific prior written permission. 166899SN/A * 176899SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186899SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196899SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206899SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216899SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226899SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236899SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246899SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256899SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266899SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276899SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286899SN/A */ 296899SN/A 307053SN/A#ifndef __CPU_RUBYTEST_RUBYTESTER_HH__ 317053SN/A#define __CPU_RUBYTEST_RUBYTESTER_HH__ 326899SN/A 337055SN/A#include <iostream> 348229Snate@binkert.org#include <string> 357454SN/A#include <vector> 367055SN/A 377632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/CheckTable.hh" 386899SN/A#include "mem/ruby/common/Global.hh" 397053SN/A#include "mem/ruby/common/SubBlock.hh" 406899SN/A#include "mem/ruby/system/RubyPort.hh" 418229Snate@binkert.org#include "mem/mem_object.hh" 428229Snate@binkert.org#include "mem/packet.hh" 436899SN/A#include "params/RubyTester.hh" 446899SN/A 457053SN/Aclass RubyTester : public MemObject 466899SN/A{ 477053SN/A public: 488922Swilliam.wang@arm.com class CpuPort : public MasterPort 497053SN/A { 507053SN/A private: 517053SN/A RubyTester *tester; 526899SN/A 537053SN/A public: 548932SBrad.Beckmann@amd.com // 558932SBrad.Beckmann@amd.com // Currently, each instatiation of the RubyTester::CpuPort supports 568932SBrad.Beckmann@amd.com // only instruction or data requests, not both. However, for those 578932SBrad.Beckmann@amd.com // RubyPorts that support both types of requests, separate InstOnly 588932SBrad.Beckmann@amd.com // and DataOnly CpuPorts will map to that RubyPort 598932SBrad.Beckmann@amd.com 609031Sandreas.hansson@arm.com CpuPort(const std::string &_name, RubyTester *_tester, PortID _id) 618965Sandreas.hansson@arm.com : MasterPort(_name, _tester, _id), tester(_tester) 627053SN/A {} 636899SN/A 647053SN/A protected: 658975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 668922Swilliam.wang@arm.com virtual void recvRetry() 678922Swilliam.wang@arm.com { panic("%s does not expect a retry\n", name()); } 687053SN/A }; 696899SN/A 707053SN/A struct SenderState : public Packet::SenderState 717053SN/A { 727053SN/A SubBlock* subBlock; 737053SN/A Packet::SenderState *saved; 746899SN/A 757053SN/A SenderState(Address addr, int size, 767053SN/A Packet::SenderState *sender_state = NULL) 777053SN/A : saved(sender_state) 787053SN/A { 797053SN/A subBlock = new SubBlock(addr, size); 807053SN/A } 816899SN/A 827053SN/A ~SenderState() 837053SN/A { 847053SN/A delete subBlock; 857053SN/A } 867053SN/A }; 876899SN/A 887053SN/A typedef RubyTesterParams Params; 897053SN/A RubyTester(const Params *p); 907053SN/A ~RubyTester(); 916899SN/A 928922Swilliam.wang@arm.com virtual MasterPort &getMasterPort(const std::string &if_name, 938922Swilliam.wang@arm.com int idx = -1); 946899SN/A 958950Sandreas.hansson@arm.com bool isInstReadableCpuPort(int idx); 968950Sandreas.hansson@arm.com 978932SBrad.Beckmann@amd.com MasterPort* getReadableCpuPort(int idx); 988932SBrad.Beckmann@amd.com MasterPort* getWritableCpuPort(int idx); 996899SN/A 1007053SN/A virtual void init(); 1016899SN/A 1027053SN/A void wakeup(); 1036899SN/A 1047053SN/A void incrementCheckCompletions() { m_checks_completed++; } 1056899SN/A 1067055SN/A void printStats(std::ostream& out) const {} 1077053SN/A void clearStats() {} 1087055SN/A void printConfig(std::ostream& out) const {} 1096899SN/A 1107055SN/A void print(std::ostream& out) const; 1118184Ssomayeh@cs.wisc.edu bool getCheckFlush() { return m_check_flush; } 1126899SN/A 1138832SAli.Saidi@ARM.com MasterID masterId() { return _masterId; } 1147053SN/A protected: 1157053SN/A class CheckStartEvent : public Event 1167053SN/A { 1177053SN/A private: 1187053SN/A RubyTester *tester; 1196899SN/A 1207053SN/A public: 1217053SN/A CheckStartEvent(RubyTester *_tester) 1227053SN/A : Event(CPU_Tick_Pri), tester(_tester) 1237053SN/A {} 1247053SN/A void process() { tester->wakeup(); } 1257053SN/A virtual const char *description() const { return "RubyTester tick"; } 1267053SN/A }; 1277053SN/A 1287053SN/A CheckStartEvent checkStartEvent; 1297053SN/A 1308832SAli.Saidi@ARM.com MasterID _masterId; 1318832SAli.Saidi@ARM.com 1326899SN/A private: 1337053SN/A void hitCallback(NodeID proc, SubBlock* data); 1346899SN/A 1357053SN/A void checkForDeadlock(); 1366899SN/A 1377053SN/A // Private copy constructor and assignment operator 1387053SN/A RubyTester(const RubyTester& obj); 1397053SN/A RubyTester& operator=(const RubyTester& obj); 1406899SN/A 1417053SN/A CheckTable* m_checkTable_ptr; 1427454SN/A std::vector<Time> m_last_progress_vector; 1436899SN/A 1448932SBrad.Beckmann@amd.com int m_num_cpus; 1457053SN/A uint64 m_checks_completed; 1468950Sandreas.hansson@arm.com std::vector<MasterPort*> writePorts; 1478950Sandreas.hansson@arm.com std::vector<MasterPort*> readPorts; 1487053SN/A uint64 m_checks_to_complete; 1497053SN/A int m_deadlock_threshold; 1508932SBrad.Beckmann@amd.com int m_num_writers; 1518932SBrad.Beckmann@amd.com int m_num_readers; 1527053SN/A int m_wakeup_frequency; 1538184Ssomayeh@cs.wisc.edu bool m_check_flush; 1548932SBrad.Beckmann@amd.com int m_num_inst_ports; 1556899SN/A}; 1566899SN/A 1577055SN/Ainline std::ostream& 1587055SN/Aoperator<<(std::ostream& out, const RubyTester& obj) 1596899SN/A{ 1607053SN/A obj.print(out); 1617055SN/A out << std::flush; 1627053SN/A return out; 1636899SN/A} 1646899SN/A 1657053SN/A#endif // __CPU_RUBYTEST_RUBYTESTER_HH__ 166