RubyTester.hh revision 13799
15390SN/A/* 25390SN/A * Copyright (c) 2013 ARM Limited 35390SN/A * All rights reserved 45390SN/A * 55390SN/A * The license below extends only to copyright in the software and shall 65390SN/A * not be construed as granting a license to any other intellectual 75390SN/A * property including but not limited to intellectual property relating 85390SN/A * to a hardware implementation of the functionality of the software 95390SN/A * licensed hereunder. You may use the software subject to the license 105390SN/A * terms below provided that you ensure that this notice is replicated 115390SN/A * unmodified and in its entirety in all distributions of the software, 125390SN/A * modified or unmodified, in source code or in binary form. 135390SN/A * 145390SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 155390SN/A * Copyright (c) 2009 Advanced Micro Devices, Inc. 165390SN/A * All rights reserved. 175390SN/A * 185390SN/A * Redistribution and use in source and binary forms, with or without 195390SN/A * modification, are permitted provided that the following conditions are 205390SN/A * met: redistributions of source code must retain the above copyright 215390SN/A * notice, this list of conditions and the following disclaimer; 225390SN/A * redistributions in binary form must reproduce the above copyright 235390SN/A * notice, this list of conditions and the following disclaimer in the 245390SN/A * documentation and/or other materials provided with the distribution; 255390SN/A * neither the name of the copyright holders nor the names of its 265390SN/A * contributors may be used to endorse or promote products derived from 275390SN/A * this software without specific prior written permission. 285390SN/A * 295390SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 305390SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 315636SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 325831Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 335643Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 345818Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 355636SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 365636SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 375833Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 385636SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 395827Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 405636SN/A */ 415390SN/A 425636SN/A#ifndef __CPU_RUBYTEST_RUBYTESTER_HH__ 435636SN/A#define __CPU_RUBYTEST_RUBYTESTER_HH__ 445636SN/A 455636SN/A#include <iostream> 465636SN/A#include <string> 475390SN/A#include <vector> 485390SN/A 495636SN/A#include "cpu/testers/rubytest/CheckTable.hh" 505636SN/A#include "mem/mem_object.hh" 515636SN/A#include "mem/packet.hh" 525636SN/A#include "mem/ruby/common/SubBlock.hh" 535636SN/A#include "mem/ruby/common/TypeDefines.hh" 545818Sgblack@eecs.umich.edu#include "params/RubyTester.hh" 555831Sgblack@eecs.umich.edu 565831Sgblack@eecs.umich.educlass RubyTester : public MemObject 575636SN/A{ 585636SN/A public: 595643Sgblack@eecs.umich.edu class CpuPort : public MasterPort 605636SN/A { 615636SN/A private: 625636SN/A RubyTester *tester; 635636SN/A // index for m_last_progress_vector and hitCallback 645818Sgblack@eecs.umich.edu PortID globalIdx; 655831Sgblack@eecs.umich.edu 665636SN/A public: 675636SN/A // 685643Sgblack@eecs.umich.edu // Currently, each instatiation of the RubyTester::CpuPort supports 695636SN/A // only instruction or data requests, not both. However, for those 705833Sgblack@eecs.umich.edu // RubyPorts that support both types of requests, separate InstOnly 715833Sgblack@eecs.umich.edu // and DataOnly CpuPorts will map to that RubyPort 725833Sgblack@eecs.umich.edu 735833Sgblack@eecs.umich.edu CpuPort(const std::string &_name, RubyTester *_tester, PortID _id, 745833Sgblack@eecs.umich.edu PortID _index) 755833Sgblack@eecs.umich.edu : MasterPort(_name, _tester, _id), tester(_tester), 765833Sgblack@eecs.umich.edu globalIdx(_index) 775833Sgblack@eecs.umich.edu {} 785833Sgblack@eecs.umich.edu 795833Sgblack@eecs.umich.edu protected: 805833Sgblack@eecs.umich.edu virtual bool recvTimingResp(PacketPtr pkt); 815833Sgblack@eecs.umich.edu virtual void recvReqRetry() 825833Sgblack@eecs.umich.edu { panic("%s does not expect a retry\n", name()); } 836432Sgblack@eecs.umich.edu }; 846432Sgblack@eecs.umich.edu 855843Sgblack@eecs.umich.edu struct SenderState : public Packet::SenderState 865843Sgblack@eecs.umich.edu { 875833Sgblack@eecs.umich.edu SubBlock subBlock; 885636SN/A 895827Sgblack@eecs.umich.edu SenderState(Addr addr, int size) : subBlock(addr, size) {} 908323Ssteve.reinhardt@amd.com 918323Ssteve.reinhardt@amd.com }; 928323Ssteve.reinhardt@amd.com 938323Ssteve.reinhardt@amd.com typedef RubyTesterParams Params; 948323Ssteve.reinhardt@amd.com RubyTester(const Params *p); 958323Ssteve.reinhardt@amd.com ~RubyTester(); 968323Ssteve.reinhardt@amd.com 978323Ssteve.reinhardt@amd.com Port &getPort(const std::string &if_name, 988323Ssteve.reinhardt@amd.com PortID idx=InvalidPortID) override; 998323Ssteve.reinhardt@amd.com 1005827Sgblack@eecs.umich.edu bool isInstOnlyCpuPort(int idx); 1015827Sgblack@eecs.umich.edu bool isInstDataCpuPort(int idx); 1025636SN/A 1035827Sgblack@eecs.umich.edu MasterPort* getReadableCpuPort(int idx); 1045636SN/A MasterPort* getWritableCpuPort(int idx); 1058839Sandreas.hansson@arm.com 1068839Sandreas.hansson@arm.com void init() override; 1078839Sandreas.hansson@arm.com 1088839Sandreas.hansson@arm.com void wakeup(); 1098839Sandreas.hansson@arm.com 1108839Sandreas.hansson@arm.com void incrementCheckCompletions() { m_checks_completed++; } 1118839Sandreas.hansson@arm.com 1128839Sandreas.hansson@arm.com void printStats(std::ostream& out) const {} 1138839Sandreas.hansson@arm.com void clearStats() {} 1148839Sandreas.hansson@arm.com void printConfig(std::ostream& out) const {} 1158839Sandreas.hansson@arm.com 1168839Sandreas.hansson@arm.com void print(std::ostream& out) const; 117 bool getCheckFlush() { return m_check_flush; } 118 119 MasterID masterId() { return _masterId; } 120 protected: 121 EventFunctionWrapper checkStartEvent; 122 123 MasterID _masterId; 124 125 private: 126 void hitCallback(NodeID proc, SubBlock* data); 127 128 void checkForDeadlock(); 129 130 // Private copy constructor and assignment operator 131 RubyTester(const RubyTester& obj); 132 RubyTester& operator=(const RubyTester& obj); 133 134 CheckTable* m_checkTable_ptr; 135 std::vector<Cycles> m_last_progress_vector; 136 137 int m_num_cpus; 138 uint64_t m_checks_completed; 139 std::vector<MasterPort*> writePorts; 140 std::vector<MasterPort*> readPorts; 141 uint64_t m_checks_to_complete; 142 int m_deadlock_threshold; 143 int m_num_writers; 144 int m_num_readers; 145 int m_wakeup_frequency; 146 bool m_check_flush; 147 int m_num_inst_only_ports; 148 int m_num_inst_data_ports; 149}; 150 151inline std::ostream& 152operator<<(std::ostream& out, const RubyTester& obj) 153{ 154 obj.print(out); 155 out << std::flush; 156 return out; 157} 158 159#endif // __CPU_RUBYTEST_RUBYTESTER_HH__ 160