RubyTester.hh revision 10713
16899SN/A/* 29542Sandreas.hansson@arm.com * Copyright (c) 2013 ARM Limited 39542Sandreas.hansson@arm.com * All rights reserved 49542Sandreas.hansson@arm.com * 59542Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 69542Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 79542Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 89542Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 99542Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 109542Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 119542Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 129542Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 139542Sandreas.hansson@arm.com * 146899SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 156899SN/A * Copyright (c) 2009 Advanced Micro Devices, Inc. 166899SN/A * All rights reserved. 176899SN/A * 186899SN/A * Redistribution and use in source and binary forms, with or without 196899SN/A * modification, are permitted provided that the following conditions are 206899SN/A * met: redistributions of source code must retain the above copyright 216899SN/A * notice, this list of conditions and the following disclaimer; 226899SN/A * redistributions in binary form must reproduce the above copyright 236899SN/A * notice, this list of conditions and the following disclaimer in the 246899SN/A * documentation and/or other materials provided with the distribution; 256899SN/A * neither the name of the copyright holders nor the names of its 266899SN/A * contributors may be used to endorse or promote products derived from 276899SN/A * this software without specific prior written permission. 286899SN/A * 296899SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306899SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316899SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326899SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336899SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346899SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356899SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366899SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376899SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386899SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396899SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406899SN/A */ 416899SN/A 427053SN/A#ifndef __CPU_RUBYTEST_RUBYTESTER_HH__ 437053SN/A#define __CPU_RUBYTEST_RUBYTESTER_HH__ 446899SN/A 457055SN/A#include <iostream> 468229Snate@binkert.org#include <string> 477454SN/A#include <vector> 487055SN/A 497632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/CheckTable.hh" 506899SN/A#include "mem/ruby/common/Global.hh" 517053SN/A#include "mem/ruby/common/SubBlock.hh" 526899SN/A#include "mem/ruby/system/RubyPort.hh" 538229Snate@binkert.org#include "mem/mem_object.hh" 548229Snate@binkert.org#include "mem/packet.hh" 556899SN/A#include "params/RubyTester.hh" 566899SN/A 577053SN/Aclass RubyTester : public MemObject 586899SN/A{ 597053SN/A public: 608922Swilliam.wang@arm.com class CpuPort : public MasterPort 617053SN/A { 627053SN/A private: 637053SN/A RubyTester *tester; 646899SN/A 657053SN/A public: 668932SBrad.Beckmann@amd.com // 678932SBrad.Beckmann@amd.com // Currently, each instatiation of the RubyTester::CpuPort supports 688932SBrad.Beckmann@amd.com // only instruction or data requests, not both. However, for those 698932SBrad.Beckmann@amd.com // RubyPorts that support both types of requests, separate InstOnly 708932SBrad.Beckmann@amd.com // and DataOnly CpuPorts will map to that RubyPort 718932SBrad.Beckmann@amd.com 729031Sandreas.hansson@arm.com CpuPort(const std::string &_name, RubyTester *_tester, PortID _id) 738965Sandreas.hansson@arm.com : MasterPort(_name, _tester, _id), tester(_tester) 747053SN/A {} 756899SN/A 767053SN/A protected: 778975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 7810713Sandreas.hansson@arm.com virtual void recvReqRetry() 798922Swilliam.wang@arm.com { panic("%s does not expect a retry\n", name()); } 807053SN/A }; 816899SN/A 827053SN/A struct SenderState : public Packet::SenderState 837053SN/A { 849542Sandreas.hansson@arm.com SubBlock subBlock; 856899SN/A 869542Sandreas.hansson@arm.com SenderState(Address addr, int size) : subBlock(addr, size) {} 876899SN/A 887053SN/A }; 896899SN/A 907053SN/A typedef RubyTesterParams Params; 917053SN/A RubyTester(const Params *p); 927053SN/A ~RubyTester(); 936899SN/A 949294Sandreas.hansson@arm.com virtual BaseMasterPort &getMasterPort(const std::string &if_name, 959294Sandreas.hansson@arm.com PortID idx = InvalidPortID); 966899SN/A 978950Sandreas.hansson@arm.com bool isInstReadableCpuPort(int idx); 988950Sandreas.hansson@arm.com 998932SBrad.Beckmann@amd.com MasterPort* getReadableCpuPort(int idx); 1008932SBrad.Beckmann@amd.com MasterPort* getWritableCpuPort(int idx); 1016899SN/A 1027053SN/A virtual void init(); 1036899SN/A 1047053SN/A void wakeup(); 1056899SN/A 1067053SN/A void incrementCheckCompletions() { m_checks_completed++; } 1076899SN/A 1087055SN/A void printStats(std::ostream& out) const {} 1097053SN/A void clearStats() {} 1107055SN/A void printConfig(std::ostream& out) const {} 1116899SN/A 1127055SN/A void print(std::ostream& out) const; 1138184Ssomayeh@cs.wisc.edu bool getCheckFlush() { return m_check_flush; } 1146899SN/A 1158832SAli.Saidi@ARM.com MasterID masterId() { return _masterId; } 1167053SN/A protected: 1177053SN/A class CheckStartEvent : public Event 1187053SN/A { 1197053SN/A private: 1207053SN/A RubyTester *tester; 1216899SN/A 1227053SN/A public: 1237053SN/A CheckStartEvent(RubyTester *_tester) 1247053SN/A : Event(CPU_Tick_Pri), tester(_tester) 1257053SN/A {} 1267053SN/A void process() { tester->wakeup(); } 1277053SN/A virtual const char *description() const { return "RubyTester tick"; } 1287053SN/A }; 1297053SN/A 1307053SN/A CheckStartEvent checkStartEvent; 1317053SN/A 1328832SAli.Saidi@ARM.com MasterID _masterId; 1338832SAli.Saidi@ARM.com 1346899SN/A private: 1357053SN/A void hitCallback(NodeID proc, SubBlock* data); 1366899SN/A 1377053SN/A void checkForDeadlock(); 1386899SN/A 1397053SN/A // Private copy constructor and assignment operator 1407053SN/A RubyTester(const RubyTester& obj); 1417053SN/A RubyTester& operator=(const RubyTester& obj); 1426899SN/A 1437053SN/A CheckTable* m_checkTable_ptr; 14410302Snilay@cs.wisc.edu std::vector<Cycles> m_last_progress_vector; 1456899SN/A 1468932SBrad.Beckmann@amd.com int m_num_cpus; 1477053SN/A uint64 m_checks_completed; 1488950Sandreas.hansson@arm.com std::vector<MasterPort*> writePorts; 1498950Sandreas.hansson@arm.com std::vector<MasterPort*> readPorts; 1507053SN/A uint64 m_checks_to_complete; 1517053SN/A int m_deadlock_threshold; 1528932SBrad.Beckmann@amd.com int m_num_writers; 1538932SBrad.Beckmann@amd.com int m_num_readers; 1547053SN/A int m_wakeup_frequency; 1558184Ssomayeh@cs.wisc.edu bool m_check_flush; 1568932SBrad.Beckmann@amd.com int m_num_inst_ports; 1576899SN/A}; 1586899SN/A 1597055SN/Ainline std::ostream& 1607055SN/Aoperator<<(std::ostream& out, const RubyTester& obj) 1616899SN/A{ 1627053SN/A obj.print(out); 1637055SN/A out << std::flush; 1647053SN/A return out; 1656899SN/A} 1666899SN/A 1677053SN/A#endif // __CPU_RUBYTEST_RUBYTESTER_HH__ 168