RubyTester.cc revision 9171
16899SN/A/*
28851Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited
38851Sandreas.hansson@arm.com * All rights reserved
48851Sandreas.hansson@arm.com *
58851Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall
68851Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual
78851Sandreas.hansson@arm.com * property including but not limited to intellectual property relating
88851Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software
98851Sandreas.hansson@arm.com * licensed hereunder.  You may use the software subject to the license
108851Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated
118851Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software,
128851Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form.
138851Sandreas.hansson@arm.com *
146899SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
156899SN/A * Copyright (c) 2009 Advanced Micro Devices, Inc.
166899SN/A * All rights reserved.
176899SN/A *
186899SN/A * Redistribution and use in source and binary forms, with or without
196899SN/A * modification, are permitted provided that the following conditions are
206899SN/A * met: redistributions of source code must retain the above copyright
216899SN/A * notice, this list of conditions and the following disclaimer;
226899SN/A * redistributions in binary form must reproduce the above copyright
236899SN/A * notice, this list of conditions and the following disclaimer in the
246899SN/A * documentation and/or other materials provided with the distribution;
256899SN/A * neither the name of the copyright holders nor the names of its
266899SN/A * contributors may be used to endorse or promote products derived from
276899SN/A * this software without specific prior written permission.
286899SN/A *
296899SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
306899SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
316899SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
326899SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
336899SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
346899SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
356899SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
366899SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
376899SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
386899SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
396899SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
406899SN/A */
416899SN/A
427805Snilay@cs.wisc.edu#include "base/misc.hh"
437632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/Check.hh"
447632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/RubyTester.hh"
458232Snate@binkert.org#include "debug/RubyTest.hh"
466899SN/A#include "mem/ruby/common/Global.hh"
477053SN/A#include "mem/ruby/common/SubBlock.hh"
486899SN/A#include "mem/ruby/system/System.hh"
496899SN/A#include "sim/sim_exit.hh"
508832SAli.Saidi@ARM.com#include "sim/system.hh"
516899SN/A
526899SN/ARubyTester::RubyTester(const Params *p)
537053SN/A  : MemObject(p), checkStartEvent(this),
548832SAli.Saidi@ARM.com    _masterId(p->system->getMasterId(name())),
558932SBrad.Beckmann@amd.com    m_num_cpus(p->num_cpus),
566899SN/A    m_checks_to_complete(p->checks_to_complete),
576899SN/A    m_deadlock_threshold(p->deadlock_threshold),
588184Ssomayeh@cs.wisc.edu    m_wakeup_frequency(p->wakeup_frequency),
598932SBrad.Beckmann@amd.com    m_check_flush(p->check_flush),
608932SBrad.Beckmann@amd.com    m_num_inst_ports(p->port_cpuInstPort_connection_count)
616899SN/A{
627053SN/A    m_checks_completed = 0;
636899SN/A
648932SBrad.Beckmann@amd.com    //
658932SBrad.Beckmann@amd.com    // Create the requested inst and data ports and place them on the
668932SBrad.Beckmann@amd.com    // appropriate read and write port lists.  The reason for the subtle
678932SBrad.Beckmann@amd.com    // difference between inst and data ports vs. read and write ports is
688932SBrad.Beckmann@amd.com    // from the tester's perspective, it only needs to know whether a port
698932SBrad.Beckmann@amd.com    // supports reads (checks) or writes (actions).  Meanwhile, the protocol
708932SBrad.Beckmann@amd.com    // controllers have data ports (support read and writes) or inst ports
718932SBrad.Beckmann@amd.com    // (support only reads).
728932SBrad.Beckmann@amd.com    // Note: the inst ports are the lowest elements of the readPort vector,
738932SBrad.Beckmann@amd.com    // then the data ports are added to the readPort vector
748932SBrad.Beckmann@amd.com    //
758932SBrad.Beckmann@amd.com    for (int i = 0; i < p->port_cpuInstPort_connection_count; ++i) {
768932SBrad.Beckmann@amd.com        readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i),
778950Sandreas.hansson@arm.com                                        this, i));
788932SBrad.Beckmann@amd.com    }
798932SBrad.Beckmann@amd.com    for (int i = 0; i < p->port_cpuDataPort_connection_count; ++i) {
808950Sandreas.hansson@arm.com        CpuPort *port = new CpuPort(csprintf("%s-dataPort%d", name(), i),
818950Sandreas.hansson@arm.com                                    this, i);
828932SBrad.Beckmann@amd.com        readPorts.push_back(port);
838932SBrad.Beckmann@amd.com        writePorts.push_back(port);
848851Sandreas.hansson@arm.com    }
858851Sandreas.hansson@arm.com
867053SN/A    // add the check start event to the event queue
877053SN/A    schedule(checkStartEvent, 1);
886899SN/A}
896899SN/A
906899SN/ARubyTester::~RubyTester()
916899SN/A{
927053SN/A    delete m_checkTable_ptr;
938932SBrad.Beckmann@amd.com    // Only delete the readPorts since the writePorts are just a subset
948932SBrad.Beckmann@amd.com    for (int i = 0; i < readPorts.size(); i++)
958932SBrad.Beckmann@amd.com        delete readPorts[i];
966899SN/A}
976899SN/A
987053SN/Avoid
997053SN/ARubyTester::init()
1006899SN/A{
1018932SBrad.Beckmann@amd.com    assert(writePorts.size() > 0 && readPorts.size() > 0);
1026899SN/A
1038932SBrad.Beckmann@amd.com    m_last_progress_vector.resize(m_num_cpus);
1047053SN/A    for (int i = 0; i < m_last_progress_vector.size(); i++) {
1057053SN/A        m_last_progress_vector[i] = 0;
1067053SN/A    }
1076899SN/A
1088932SBrad.Beckmann@amd.com    m_num_writers = writePorts.size();
1098932SBrad.Beckmann@amd.com    m_num_readers = readPorts.size();
1106899SN/A
1118932SBrad.Beckmann@amd.com    m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this);
1126899SN/A}
1136899SN/A
1148922Swilliam.wang@arm.comMasterPort &
1158922Swilliam.wang@arm.comRubyTester::getMasterPort(const std::string &if_name, int idx)
1166899SN/A{
1178932SBrad.Beckmann@amd.com    if (if_name != "cpuInstPort" && if_name != "cpuDataPort") {
1188922Swilliam.wang@arm.com        // pass it along to our super class
1198922Swilliam.wang@arm.com        return MemObject::getMasterPort(if_name, idx);
1208922Swilliam.wang@arm.com    } else {
1218932SBrad.Beckmann@amd.com        if (if_name == "cpuInstPort") {
1228932SBrad.Beckmann@amd.com            if (idx > m_num_inst_ports) {
1238932SBrad.Beckmann@amd.com                panic("RubyTester::getMasterPort: unknown inst port idx %d\n",
1248932SBrad.Beckmann@amd.com                      idx);
1258932SBrad.Beckmann@amd.com            }
1268932SBrad.Beckmann@amd.com            //
1278932SBrad.Beckmann@amd.com            // inst ports directly map to the lowest readPort elements
1288932SBrad.Beckmann@amd.com            //
1298932SBrad.Beckmann@amd.com            return *readPorts[idx];
1308932SBrad.Beckmann@amd.com        } else {
1318932SBrad.Beckmann@amd.com            assert(if_name == "cpuDataPort");
1328932SBrad.Beckmann@amd.com            //
1338932SBrad.Beckmann@amd.com            // add the inst port offset to translate to the correct read port
1348932SBrad.Beckmann@amd.com            // index
1358932SBrad.Beckmann@amd.com            //
1368932SBrad.Beckmann@amd.com            int read_idx = idx + m_num_inst_ports;
1378932SBrad.Beckmann@amd.com            if (read_idx >= static_cast<int>(readPorts.size())) {
1388932SBrad.Beckmann@amd.com                panic("RubyTester::getMasterPort: unknown data port idx %d\n",
1398932SBrad.Beckmann@amd.com                      idx);
1408932SBrad.Beckmann@amd.com            }
1418932SBrad.Beckmann@amd.com            return *readPorts[read_idx];
1428922Swilliam.wang@arm.com        }
1436899SN/A    }
1446899SN/A}
1456899SN/A
1466899SN/Abool
1478975Sandreas.hansson@arm.comRubyTester::CpuPort::recvTimingResp(PacketPtr pkt)
1486899SN/A{
1497053SN/A    // retrieve the subblock and call hitCallback
1507053SN/A    RubyTester::SenderState* senderState =
1517053SN/A        safe_cast<RubyTester::SenderState*>(pkt->senderState);
1527053SN/A    SubBlock* subblock = senderState->subBlock;
1537053SN/A    assert(subblock != NULL);
1546899SN/A
1557053SN/A    // pop the sender state from the packet
1567053SN/A    pkt->senderState = senderState->saved;
1576899SN/A
1588965Sandreas.hansson@arm.com    tester->hitCallback(id, subblock);
1597053SN/A
1607053SN/A    // Now that the tester has completed, delete the senderState
1617053SN/A    // (includes sublock) and the packet, then return
1627053SN/A    delete senderState;
1637053SN/A    delete pkt->req;
1647053SN/A    delete pkt;
1657053SN/A    return true;
1666899SN/A}
1676899SN/A
1688950Sandreas.hansson@arm.combool
1698950Sandreas.hansson@arm.comRubyTester::isInstReadableCpuPort(int idx)
1708950Sandreas.hansson@arm.com{
1718950Sandreas.hansson@arm.com    return idx < m_num_inst_ports;
1728950Sandreas.hansson@arm.com}
1738950Sandreas.hansson@arm.com
1748922Swilliam.wang@arm.comMasterPort*
1758932SBrad.Beckmann@amd.comRubyTester::getReadableCpuPort(int idx)
1766899SN/A{
1778932SBrad.Beckmann@amd.com    assert(idx >= 0 && idx < readPorts.size());
1786899SN/A
1798932SBrad.Beckmann@amd.com    return readPorts[idx];
1808932SBrad.Beckmann@amd.com}
1818932SBrad.Beckmann@amd.com
1828932SBrad.Beckmann@amd.comMasterPort*
1838932SBrad.Beckmann@amd.comRubyTester::getWritableCpuPort(int idx)
1848932SBrad.Beckmann@amd.com{
1858932SBrad.Beckmann@amd.com    assert(idx >= 0 && idx < writePorts.size());
1868932SBrad.Beckmann@amd.com
1878932SBrad.Beckmann@amd.com    return writePorts[idx];
1886899SN/A}
1896899SN/A
1907053SN/Avoid
1917053SN/ARubyTester::hitCallback(NodeID proc, SubBlock* data)
1926899SN/A{
1937053SN/A    // Mark that we made progress
1949171Snilay@cs.wisc.edu    m_last_progress_vector[proc] = g_system_ptr->getTime();
1956899SN/A
1967053SN/A    DPRINTF(RubyTest, "completed request for proc: %d\n", proc);
1977053SN/A    DPRINTF(RubyTest, "addr: 0x%x, size: %d, data: ",
1987053SN/A            data->getAddress(), data->getSize());
1997053SN/A    for (int byte = 0; byte < data->getSize(); byte++) {
2007053SN/A        DPRINTF(RubyTest, "%d", data->getByte(byte));
2017053SN/A    }
2027053SN/A    DPRINTF(RubyTest, "\n");
2036899SN/A
2047053SN/A    // This tells us our store has 'completed' or for a load gives us
2057053SN/A    // back the data to make the check
2067053SN/A    Check* check_ptr = m_checkTable_ptr->getCheck(data->getAddress());
2077053SN/A    assert(check_ptr != NULL);
2087053SN/A    check_ptr->performCallback(proc, data);
2096899SN/A}
2106899SN/A
2117053SN/Avoid
2127053SN/ARubyTester::wakeup()
2137053SN/A{
2147053SN/A    if (m_checks_completed < m_checks_to_complete) {
2157053SN/A        // Try to perform an action or check
2167053SN/A        Check* check_ptr = m_checkTable_ptr->getRandomCheck();
2177053SN/A        assert(check_ptr != NULL);
2187053SN/A        check_ptr->initiate();
2197053SN/A
2207053SN/A        checkForDeadlock();
2217053SN/A
2227823Ssteve.reinhardt@amd.com        schedule(checkStartEvent, curTick() + m_wakeup_frequency);
2237053SN/A    } else {
2247053SN/A        exitSimLoop("Ruby Tester completed");
2257053SN/A    }
2266899SN/A}
2276899SN/A
2287053SN/Avoid
2297053SN/ARubyTester::checkForDeadlock()
2306899SN/A{
2317053SN/A    int size = m_last_progress_vector.size();
2329171Snilay@cs.wisc.edu    Time current_time = g_system_ptr->getTime();
2337053SN/A    for (int processor = 0; processor < size; processor++) {
2347053SN/A        if ((current_time - m_last_progress_vector[processor]) >
2357053SN/A                m_deadlock_threshold) {
2367805Snilay@cs.wisc.edu            panic("Deadlock detected: current_time: %d last_progress_time: %d "
2377805Snilay@cs.wisc.edu                  "difference:  %d processor: %d\n",
2387805Snilay@cs.wisc.edu                  current_time, m_last_progress_vector[processor],
2397805Snilay@cs.wisc.edu                  current_time - m_last_progress_vector[processor], processor);
2407053SN/A        }
2416899SN/A    }
2426899SN/A}
2436899SN/A
2447053SN/Avoid
2457055SN/ARubyTester::print(std::ostream& out) const
2466899SN/A{
2477055SN/A    out << "[RubyTester]" << std::endl;
2486899SN/A}
2496899SN/A
2506899SN/ARubyTester *
2516899SN/ARubyTesterParams::create()
2526899SN/A{
2536899SN/A    return new RubyTester(this);
2546899SN/A}
255