Check.cc revision 8184
16899SN/A/* 26899SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 36899SN/A * Copyright (c) 2009 Advanced Micro Devices, Inc. 46899SN/A * All rights reserved. 56899SN/A * 66899SN/A * Redistribution and use in source and binary forms, with or without 76899SN/A * modification, are permitted provided that the following conditions are 86899SN/A * met: redistributions of source code must retain the above copyright 96899SN/A * notice, this list of conditions and the following disclaimer; 106899SN/A * redistributions in binary form must reproduce the above copyright 116899SN/A * notice, this list of conditions and the following disclaimer in the 126899SN/A * documentation and/or other materials provided with the distribution; 136899SN/A * neither the name of the copyright holders nor the names of its 146899SN/A * contributors may be used to endorse or promote products derived from 156899SN/A * this software without specific prior written permission. 166899SN/A * 176899SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186899SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196899SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206899SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216899SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226899SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236899SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246899SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256899SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266899SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276899SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286899SN/A */ 296899SN/A 307632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/Check.hh" 317053SN/A#include "mem/ruby/common/SubBlock.hh" 326899SN/A#include "mem/ruby/system/Sequencer.hh" 336899SN/A#include "mem/ruby/system/System.hh" 346899SN/A 357053SN/Atypedef RubyTester::SenderState SenderState; 367053SN/A 377053SN/ACheck::Check(const Address& address, const Address& pc, 387053SN/A int _num_cpu_sequencers, RubyTester* _tester) 397053SN/A : m_num_cpu_sequencers(_num_cpu_sequencers), m_tester_ptr(_tester) 406899SN/A{ 417053SN/A m_status = TesterStatus_Idle; 426899SN/A 437053SN/A pickValue(); 447053SN/A pickInitiatingNode(); 457053SN/A changeAddress(address); 467053SN/A m_pc = pc; 478164Snilay@cs.wisc.edu m_access_mode = RubyAccessMode(random() % RubyAccessMode_NUM); 487053SN/A m_store_count = 0; 496899SN/A} 506899SN/A 517053SN/Avoid 527053SN/ACheck::initiate() 536899SN/A{ 547053SN/A DPRINTF(RubyTest, "initiating\n"); 557053SN/A debugPrint(); 566899SN/A 577053SN/A // currently no protocols support prefetches 587053SN/A if (false && (random() & 0xf) == 0) { 597053SN/A initiatePrefetch(); // Prefetch from random processor 607053SN/A } 616899SN/A 628184Ssomayeh@cs.wisc.edu if (m_tester_ptr->getCheckFlush() && (random() & 0xff) == 0) { 638184Ssomayeh@cs.wisc.edu initiateFlush(); // issue a Flush request from random processor 648184Ssomayeh@cs.wisc.edu } 658184Ssomayeh@cs.wisc.edu 667053SN/A if (m_status == TesterStatus_Idle) { 677053SN/A initiateAction(); 687053SN/A } else if (m_status == TesterStatus_Ready) { 697053SN/A initiateCheck(); 707053SN/A } else { 717053SN/A // Pending - do nothing 727053SN/A DPRINTF(RubyTest, 737053SN/A "initiating action/check - failed: action/check is pending\n"); 747053SN/A } 756899SN/A} 766899SN/A 777053SN/Avoid 787053SN/ACheck::initiatePrefetch() 796899SN/A{ 807053SN/A DPRINTF(RubyTest, "initiating prefetch\n"); 816899SN/A 827053SN/A int index = random() % m_num_cpu_sequencers; 837053SN/A RubyTester::CpuPort* port = 847053SN/A safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index)); 856899SN/A 867053SN/A Request::Flags flags; 877053SN/A flags.set(Request::PREFETCH); 886899SN/A 897053SN/A Packet::Command cmd; 906899SN/A 917053SN/A // 1 in 8 chance this will be an exclusive prefetch 927053SN/A if ((random() & 0x7) != 0) { 937053SN/A cmd = MemCmd::ReadReq; 947053SN/A 957053SN/A // 50% chance that the request will be an instruction fetch 967053SN/A if ((random() & 0x1) == 0) { 977053SN/A flags.set(Request::INST_FETCH); 987053SN/A } 997053SN/A } else { 1007053SN/A cmd = MemCmd::WriteReq; 1017053SN/A flags.set(Request::PF_EXCLUSIVE); 1026899SN/A } 1036899SN/A 1047568SN/A // Prefetches are assumed to be 0 sized 1057823Ssteve.reinhardt@amd.com Request *req = new Request(m_address.getAddress(), 0, flags, curTick(), 1067568SN/A m_pc.getAddress()); 1077568SN/A 1087053SN/A PacketPtr pkt = new Packet(req, cmd, port->idx); 1096899SN/A 1107053SN/A // push the subblock onto the sender state. The sequencer will 1117053SN/A // update the subblock on the return 1127053SN/A pkt->senderState = 1137053SN/A new SenderState(m_address, req->getSize(), pkt->senderState); 1146899SN/A 1157053SN/A if (port->sendTiming(pkt)) { 1167053SN/A DPRINTF(RubyTest, "successfully initiated prefetch.\n"); 1177053SN/A } else { 1187053SN/A // If the packet did not issue, must delete 1197053SN/A SenderState* senderState = safe_cast<SenderState*>(pkt->senderState); 1207053SN/A pkt->senderState = senderState->saved; 1217053SN/A delete senderState; 1227053SN/A delete pkt->req; 1237053SN/A delete pkt; 1246899SN/A 1257053SN/A DPRINTF(RubyTest, 1267053SN/A "prefetch initiation failed because Port was busy.\n"); 1277053SN/A } 1286899SN/A} 1296899SN/A 1307053SN/Avoid 1318184Ssomayeh@cs.wisc.eduCheck::initiateFlush() 1328184Ssomayeh@cs.wisc.edu{ 1338184Ssomayeh@cs.wisc.edu 1348184Ssomayeh@cs.wisc.edu DPRINTF(RubyTest, "initiating Flush\n"); 1358184Ssomayeh@cs.wisc.edu 1368184Ssomayeh@cs.wisc.edu int index = random() % m_num_cpu_sequencers; 1378184Ssomayeh@cs.wisc.edu RubyTester::CpuPort* port = 1388184Ssomayeh@cs.wisc.edu safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index)); 1398184Ssomayeh@cs.wisc.edu 1408184Ssomayeh@cs.wisc.edu Request::Flags flags; 1418184Ssomayeh@cs.wisc.edu 1428184Ssomayeh@cs.wisc.edu Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags, curTick(), 1438184Ssomayeh@cs.wisc.edu m_pc.getAddress()); 1448184Ssomayeh@cs.wisc.edu 1458184Ssomayeh@cs.wisc.edu Packet::Command cmd; 1468184Ssomayeh@cs.wisc.edu 1478184Ssomayeh@cs.wisc.edu cmd = MemCmd::FlushReq; 1488184Ssomayeh@cs.wisc.edu 1498184Ssomayeh@cs.wisc.edu PacketPtr pkt = new Packet(req, cmd, port->idx); 1508184Ssomayeh@cs.wisc.edu 1518184Ssomayeh@cs.wisc.edu // push the subblock onto the sender state. The sequencer will 1528184Ssomayeh@cs.wisc.edu // update the subblock on the return 1538184Ssomayeh@cs.wisc.edu pkt->senderState = 1548184Ssomayeh@cs.wisc.edu new SenderState(m_address, req->getSize(), pkt->senderState); 1558184Ssomayeh@cs.wisc.edu 1568184Ssomayeh@cs.wisc.edu if (port->sendTiming(pkt)) { 1578184Ssomayeh@cs.wisc.edu DPRINTF(RubyTest, "initiating Flush - successful\n"); 1588184Ssomayeh@cs.wisc.edu } 1598184Ssomayeh@cs.wisc.edu} 1608184Ssomayeh@cs.wisc.edu 1618184Ssomayeh@cs.wisc.eduvoid 1627053SN/ACheck::initiateAction() 1636899SN/A{ 1647053SN/A DPRINTF(RubyTest, "initiating Action\n"); 1657053SN/A assert(m_status == TesterStatus_Idle); 1666899SN/A 1677053SN/A int index = random() % m_num_cpu_sequencers; 1687053SN/A RubyTester::CpuPort* port = 1697053SN/A safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index)); 1706899SN/A 1717053SN/A Request::Flags flags; 1726899SN/A 1737053SN/A // Create the particular address for the next byte to be written 1747053SN/A Address writeAddr(m_address.getAddress() + m_store_count); 1756899SN/A 1767053SN/A // Stores are assumed to be 1 byte-sized 1777823Ssteve.reinhardt@amd.com Request *req = new Request(writeAddr.getAddress(), 1, flags, curTick(), 1787053SN/A m_pc.getAddress()); 1796899SN/A 1807053SN/A Packet::Command cmd; 1817053SN/A 1827053SN/A // 1 out of 8 chance, issue an atomic rather than a write 1837053SN/A // if ((random() & 0x7) == 0) { 1847053SN/A // cmd = MemCmd::SwapReq; 1857053SN/A // } else { 1866899SN/A cmd = MemCmd::WriteReq; 1877053SN/A // } 1886899SN/A 1897053SN/A PacketPtr pkt = new Packet(req, cmd, port->idx); 1907053SN/A uint8_t* writeData = new uint8_t; 1917053SN/A *writeData = m_value + m_store_count; 1927053SN/A pkt->dataDynamic(writeData); 1936899SN/A 1947053SN/A DPRINTF(RubyTest, "data 0x%x check 0x%x\n", 1957053SN/A *(pkt->getPtr<uint8_t>()), *writeData); 1966899SN/A 1977053SN/A // push the subblock onto the sender state. The sequencer will 1987053SN/A // update the subblock on the return 1997053SN/A pkt->senderState = 2007053SN/A new SenderState(writeAddr, req->getSize(), pkt->senderState); 2016899SN/A 2027053SN/A if (port->sendTiming(pkt)) { 2037053SN/A DPRINTF(RubyTest, "initiating action - successful\n"); 2047053SN/A DPRINTF(RubyTest, "status before action update: %s\n", 2057053SN/A (TesterStatus_to_string(m_status)).c_str()); 2067053SN/A m_status = TesterStatus_Action_Pending; 2077053SN/A } else { 2087053SN/A // If the packet did not issue, must delete 2097053SN/A // Note: No need to delete the data, the packet destructor 2107053SN/A // will delete it 2117053SN/A SenderState* senderState = safe_cast<SenderState*>(pkt->senderState); 2127053SN/A pkt->senderState = senderState->saved; 2137053SN/A delete senderState; 2147053SN/A delete pkt->req; 2157053SN/A delete pkt; 2167053SN/A 2177053SN/A DPRINTF(RubyTest, "failed to initiate action - sequencer not ready\n"); 2187053SN/A } 2197053SN/A 2207053SN/A DPRINTF(RubyTest, "status after action update: %s\n", 2216899SN/A (TesterStatus_to_string(m_status)).c_str()); 2226899SN/A} 2236899SN/A 2247053SN/Avoid 2257053SN/ACheck::initiateCheck() 2266899SN/A{ 2277053SN/A DPRINTF(RubyTest, "Initiating Check\n"); 2287053SN/A assert(m_status == TesterStatus_Ready); 2296899SN/A 2307053SN/A int index = random() % m_num_cpu_sequencers; 2317053SN/A RubyTester::CpuPort* port = 2327053SN/A safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index)); 2336899SN/A 2347053SN/A Request::Flags flags; 2356899SN/A 2367053SN/A // 50% chance that the request will be an instruction fetch 2377053SN/A if ((random() & 0x1) == 0) { 2387053SN/A flags.set(Request::INST_FETCH); 2397053SN/A } 2406899SN/A 2417568SN/A // Checks are sized depending on the number of bytes written 2427568SN/A Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags, 2437823Ssteve.reinhardt@amd.com curTick(), m_pc.getAddress()); 2447568SN/A 2457053SN/A PacketPtr pkt = new Packet(req, MemCmd::ReadReq, port->idx); 2467053SN/A uint8_t* dataArray = new uint8_t[CHECK_SIZE]; 2477053SN/A pkt->dataDynamicArray(dataArray); 2486899SN/A 2497053SN/A // push the subblock onto the sender state. The sequencer will 2507053SN/A // update the subblock on the return 2517053SN/A pkt->senderState = 2527053SN/A new SenderState(m_address, req->getSize(), pkt->senderState); 2536899SN/A 2547053SN/A if (port->sendTiming(pkt)) { 2557053SN/A DPRINTF(RubyTest, "initiating check - successful\n"); 2567053SN/A DPRINTF(RubyTest, "status before check update: %s\n", 2577053SN/A TesterStatus_to_string(m_status).c_str()); 2587053SN/A m_status = TesterStatus_Check_Pending; 2597053SN/A } else { 2607053SN/A // If the packet did not issue, must delete 2617053SN/A // Note: No need to delete the data, the packet destructor 2627053SN/A // will delete it 2637053SN/A SenderState* senderState = safe_cast<SenderState*>(pkt->senderState); 2647053SN/A pkt->senderState = senderState->saved; 2657053SN/A delete senderState; 2667053SN/A delete pkt->req; 2677053SN/A delete pkt; 2686899SN/A 2697053SN/A DPRINTF(RubyTest, "failed to initiate check - cpu port not ready\n"); 2707053SN/A } 2717053SN/A 2727053SN/A DPRINTF(RubyTest, "status after check update: %s\n", 2737053SN/A TesterStatus_to_string(m_status).c_str()); 2746899SN/A} 2756899SN/A 2767053SN/Avoid 2777053SN/ACheck::performCallback(NodeID proc, SubBlock* data) 2786899SN/A{ 2797053SN/A Address address = data->getAddress(); 2806899SN/A 2817053SN/A // This isn't exactly right since we now have multi-byte checks 2827053SN/A // assert(getAddress() == address); 2836899SN/A 2847053SN/A assert(getAddress().getLineAddress() == address.getLineAddress()); 2857053SN/A assert(data != NULL); 2867053SN/A 2877053SN/A DPRINTF(RubyTest, "RubyTester Callback\n"); 2886899SN/A debugPrint(); 2896899SN/A 2907053SN/A if (m_status == TesterStatus_Action_Pending) { 2917053SN/A DPRINTF(RubyTest, "Action callback write value: %d, currently %d\n", 2927053SN/A (m_value + m_store_count), data->getByte(0)); 2937053SN/A // Perform store one byte at a time 2947053SN/A data->setByte(0, (m_value + m_store_count)); 2957053SN/A m_store_count++; 2967053SN/A if (m_store_count == CHECK_SIZE) { 2977053SN/A m_status = TesterStatus_Ready; 2987053SN/A } else { 2997053SN/A m_status = TesterStatus_Idle; 3007053SN/A } 3017053SN/A DPRINTF(RubyTest, "Action callback return data now %d\n", 3027053SN/A data->getByte(0)); 3037053SN/A } else if (m_status == TesterStatus_Check_Pending) { 3047053SN/A DPRINTF(RubyTest, "Check callback\n"); 3057053SN/A // Perform load/check 3067053SN/A for (int byte_number=0; byte_number<CHECK_SIZE; byte_number++) { 3077053SN/A if (uint8(m_value + byte_number) != data->getByte(byte_number)) { 3087805Snilay@cs.wisc.edu panic("Action/check failure: proc: %d address: %s data: %s " 3097805Snilay@cs.wisc.edu "byte_number: %d m_value+byte_number: %d byte: %d %s" 3107805Snilay@cs.wisc.edu "Time: %d\n", 3117805Snilay@cs.wisc.edu proc, address, data, byte_number, 3127805Snilay@cs.wisc.edu (int)m_value + byte_number, 3137805Snilay@cs.wisc.edu (int)data->getByte(byte_number), *this, 3147805Snilay@cs.wisc.edu g_eventQueue_ptr->getTime()); 3157053SN/A } 3167053SN/A } 3177053SN/A DPRINTF(RubyTest, "Action/check success\n"); 3187053SN/A debugPrint(); 3196899SN/A 3207053SN/A // successful check complete, increment complete 3217053SN/A m_tester_ptr->incrementCheckCompletions(); 3226899SN/A 3237053SN/A m_status = TesterStatus_Idle; 3247053SN/A pickValue(); 3257053SN/A 3267053SN/A } else { 3277805Snilay@cs.wisc.edu panic("Unexpected TesterStatus: %s proc: %d data: %s m_status: %s " 3287805Snilay@cs.wisc.edu "time: %d\n", 3297805Snilay@cs.wisc.edu *this, proc, data, m_status, g_eventQueue_ptr->getTime()); 3307053SN/A } 3317053SN/A 3327053SN/A DPRINTF(RubyTest, "proc: %d, Address: 0x%x\n", proc, 3337053SN/A getAddress().getLineAddress()); 3347053SN/A DPRINTF(RubyTest, "Callback done\n"); 3357053SN/A debugPrint(); 3366899SN/A} 3376899SN/A 3387053SN/Avoid 3397053SN/ACheck::changeAddress(const Address& address) 3406899SN/A{ 3417053SN/A assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready); 3427053SN/A m_status = TesterStatus_Idle; 3437053SN/A m_address = address; 3447053SN/A m_store_count = 0; 3456899SN/A} 3466899SN/A 3477053SN/Avoid 3487053SN/ACheck::pickValue() 3496899SN/A{ 3507053SN/A assert(m_status == TesterStatus_Idle); 3517053SN/A m_status = TesterStatus_Idle; 3527053SN/A m_value = random() & 0xff; // One byte 3537053SN/A m_store_count = 0; 3546899SN/A} 3556899SN/A 3567053SN/Avoid 3577053SN/ACheck::pickInitiatingNode() 3586899SN/A{ 3597053SN/A assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready); 3607053SN/A m_status = TesterStatus_Idle; 3617053SN/A m_initiatingNode = (random() % m_num_cpu_sequencers); 3627053SN/A DPRINTF(RubyTest, "picked initiating node %d\n", m_initiatingNode); 3637053SN/A m_store_count = 0; 3646899SN/A} 3656899SN/A 3667053SN/Avoid 3677055SN/ACheck::print(std::ostream& out) const 3686899SN/A{ 3697053SN/A out << "[" 3707053SN/A << m_address << ", value: " 3717053SN/A << (int)m_value << ", status: " 3727053SN/A << m_status << ", initiating node: " 3737053SN/A << m_initiatingNode << ", store_count: " 3747053SN/A << m_store_count 3757055SN/A << "]" << std::flush; 3766899SN/A} 3776899SN/A 3787053SN/Avoid 3797053SN/ACheck::debugPrint() 3806899SN/A{ 3817053SN/A DPRINTF(RubyTest, 3827053SN/A "[%#x, value: %d, status: %s, initiating node: %d, store_count: %d]\n", 3837053SN/A m_address.getAddress(), (int)m_value, 3847053SN/A TesterStatus_to_string(m_status).c_str(), 3857053SN/A m_initiatingNode, m_store_count); 3866899SN/A} 387