Check.cc revision 11266
16899SN/A/* 26899SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 36899SN/A * Copyright (c) 2009 Advanced Micro Devices, Inc. 46899SN/A * All rights reserved. 56899SN/A * 66899SN/A * Redistribution and use in source and binary forms, with or without 76899SN/A * modification, are permitted provided that the following conditions are 86899SN/A * met: redistributions of source code must retain the above copyright 96899SN/A * notice, this list of conditions and the following disclaimer; 106899SN/A * redistributions in binary form must reproduce the above copyright 116899SN/A * notice, this list of conditions and the following disclaimer in the 126899SN/A * documentation and/or other materials provided with the distribution; 136899SN/A * neither the name of the copyright holders nor the names of its 146899SN/A * contributors may be used to endorse or promote products derived from 156899SN/A * this software without specific prior written permission. 166899SN/A * 176899SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186899SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196899SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206899SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216899SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226899SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236899SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246899SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256899SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266899SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276899SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286899SN/A */ 296899SN/A 3010348Sandreas.hansson@arm.com#include "base/random.hh" 317632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/Check.hh" 328232Snate@binkert.org#include "debug/RubyTest.hh" 337053SN/A#include "mem/ruby/common/SubBlock.hh" 346899SN/A 357053SN/Atypedef RubyTester::SenderState SenderState; 367053SN/A 3711025Snilay@cs.wisc.eduCheck::Check(Addr address, Addr pc, int _num_writers, int _num_readers, 3811025Snilay@cs.wisc.edu RubyTester* _tester) 398932SBrad.Beckmann@amd.com : m_num_writers(_num_writers), m_num_readers(_num_readers), 408932SBrad.Beckmann@amd.com m_tester_ptr(_tester) 416899SN/A{ 427053SN/A m_status = TesterStatus_Idle; 436899SN/A 447053SN/A pickValue(); 457053SN/A pickInitiatingNode(); 467053SN/A changeAddress(address); 477053SN/A m_pc = pc; 4810348Sandreas.hansson@arm.com m_access_mode = RubyAccessMode(random_mt.random(0, 4910348Sandreas.hansson@arm.com RubyAccessMode_NUM - 1)); 507053SN/A m_store_count = 0; 516899SN/A} 526899SN/A 537053SN/Avoid 547053SN/ACheck::initiate() 556899SN/A{ 567053SN/A DPRINTF(RubyTest, "initiating\n"); 577053SN/A debugPrint(); 586899SN/A 597053SN/A // currently no protocols support prefetches 6010348Sandreas.hansson@arm.com if (false && (random_mt.random(0, 0xf) == 0)) { 617053SN/A initiatePrefetch(); // Prefetch from random processor 627053SN/A } 636899SN/A 6410348Sandreas.hansson@arm.com if (m_tester_ptr->getCheckFlush() && (random_mt.random(0, 0xff) == 0)) { 658184Ssomayeh@cs.wisc.edu initiateFlush(); // issue a Flush request from random processor 668184Ssomayeh@cs.wisc.edu } 678184Ssomayeh@cs.wisc.edu 687053SN/A if (m_status == TesterStatus_Idle) { 697053SN/A initiateAction(); 707053SN/A } else if (m_status == TesterStatus_Ready) { 717053SN/A initiateCheck(); 727053SN/A } else { 737053SN/A // Pending - do nothing 747053SN/A DPRINTF(RubyTest, 757053SN/A "initiating action/check - failed: action/check is pending\n"); 767053SN/A } 776899SN/A} 786899SN/A 797053SN/Avoid 807053SN/ACheck::initiatePrefetch() 816899SN/A{ 827053SN/A DPRINTF(RubyTest, "initiating prefetch\n"); 836899SN/A 8410348Sandreas.hansson@arm.com int index = random_mt.random(0, m_num_readers - 1); 858950Sandreas.hansson@arm.com MasterPort* port = m_tester_ptr->getReadableCpuPort(index); 866899SN/A 877053SN/A Request::Flags flags; 887053SN/A flags.set(Request::PREFETCH); 896899SN/A 907053SN/A Packet::Command cmd; 916899SN/A 927053SN/A // 1 in 8 chance this will be an exclusive prefetch 9310348Sandreas.hansson@arm.com if (random_mt.random(0, 0x7) != 0) { 947053SN/A cmd = MemCmd::ReadReq; 957053SN/A 968932SBrad.Beckmann@amd.com // if necessary, make the request an instruction fetch 9711266SBrad.Beckmann@amd.com if (m_tester_ptr->isInstOnlyCpuPort(index) || 9811266SBrad.Beckmann@amd.com (m_tester_ptr->isInstDataCpuPort(index) && 9911266SBrad.Beckmann@amd.com (random_mt.random(0, 0x1)))) { 1007053SN/A flags.set(Request::INST_FETCH); 1017053SN/A } 1027053SN/A } else { 1037053SN/A cmd = MemCmd::WriteReq; 1047053SN/A flags.set(Request::PF_EXCLUSIVE); 1056899SN/A } 1066899SN/A 1077568SN/A // Prefetches are assumed to be 0 sized 10811025Snilay@cs.wisc.edu Request *req = new Request(m_address, 0, flags, 10911025Snilay@cs.wisc.edu m_tester_ptr->masterId(), curTick(), m_pc); 1108190SLisa.Hsu@amd.com req->setThreadContext(index, 0); 1117568SN/A 1128949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, cmd); 11310562Sandreas.hansson@arm.com // despite the oddity of the 0 size (questionable if this should 11410562Sandreas.hansson@arm.com // even be allowed), a prefetch is still a read and as such needs 11510562Sandreas.hansson@arm.com // a place to store the result 11610566Sandreas.hansson@arm.com uint8_t *data = new uint8_t[1]; 11710562Sandreas.hansson@arm.com pkt->dataDynamic(data); 1186899SN/A 1197053SN/A // push the subblock onto the sender state. The sequencer will 1207053SN/A // update the subblock on the return 1219542Sandreas.hansson@arm.com pkt->senderState = new SenderState(m_address, req->getSize()); 1226899SN/A 1238975Sandreas.hansson@arm.com if (port->sendTimingReq(pkt)) { 1247053SN/A DPRINTF(RubyTest, "successfully initiated prefetch.\n"); 1257053SN/A } else { 1267053SN/A // If the packet did not issue, must delete 1279542Sandreas.hansson@arm.com delete pkt->senderState; 1287053SN/A delete pkt->req; 1297053SN/A delete pkt; 1306899SN/A 1317053SN/A DPRINTF(RubyTest, 1327053SN/A "prefetch initiation failed because Port was busy.\n"); 1337053SN/A } 1346899SN/A} 1356899SN/A 1367053SN/Avoid 1378184Ssomayeh@cs.wisc.eduCheck::initiateFlush() 1388184Ssomayeh@cs.wisc.edu{ 1398184Ssomayeh@cs.wisc.edu 1408184Ssomayeh@cs.wisc.edu DPRINTF(RubyTest, "initiating Flush\n"); 1418184Ssomayeh@cs.wisc.edu 14210348Sandreas.hansson@arm.com int index = random_mt.random(0, m_num_writers - 1); 1438950Sandreas.hansson@arm.com MasterPort* port = m_tester_ptr->getWritableCpuPort(index); 1448184Ssomayeh@cs.wisc.edu 1458184Ssomayeh@cs.wisc.edu Request::Flags flags; 1468184Ssomayeh@cs.wisc.edu 14711025Snilay@cs.wisc.edu Request *req = new Request(m_address, CHECK_SIZE, flags, 14811025Snilay@cs.wisc.edu m_tester_ptr->masterId(), curTick(), m_pc); 1498184Ssomayeh@cs.wisc.edu 1508184Ssomayeh@cs.wisc.edu Packet::Command cmd; 1518184Ssomayeh@cs.wisc.edu 1528184Ssomayeh@cs.wisc.edu cmd = MemCmd::FlushReq; 1538184Ssomayeh@cs.wisc.edu 1548949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, cmd); 1558184Ssomayeh@cs.wisc.edu 1568184Ssomayeh@cs.wisc.edu // push the subblock onto the sender state. The sequencer will 1578184Ssomayeh@cs.wisc.edu // update the subblock on the return 1589542Sandreas.hansson@arm.com pkt->senderState = new SenderState(m_address, req->getSize()); 1598184Ssomayeh@cs.wisc.edu 1608975Sandreas.hansson@arm.com if (port->sendTimingReq(pkt)) { 1618184Ssomayeh@cs.wisc.edu DPRINTF(RubyTest, "initiating Flush - successful\n"); 1628184Ssomayeh@cs.wisc.edu } 1638184Ssomayeh@cs.wisc.edu} 1648184Ssomayeh@cs.wisc.edu 1658184Ssomayeh@cs.wisc.eduvoid 1667053SN/ACheck::initiateAction() 1676899SN/A{ 1687053SN/A DPRINTF(RubyTest, "initiating Action\n"); 1697053SN/A assert(m_status == TesterStatus_Idle); 1706899SN/A 17110348Sandreas.hansson@arm.com int index = random_mt.random(0, m_num_writers - 1); 1728950Sandreas.hansson@arm.com MasterPort* port = m_tester_ptr->getWritableCpuPort(index); 1736899SN/A 1747053SN/A Request::Flags flags; 1756899SN/A 1767053SN/A // Create the particular address for the next byte to be written 17711025Snilay@cs.wisc.edu Addr writeAddr(m_address + m_store_count); 1786899SN/A 1797053SN/A // Stores are assumed to be 1 byte-sized 18011025Snilay@cs.wisc.edu Request *req = new Request(writeAddr, 1, flags, m_tester_ptr->masterId(), 18111025Snilay@cs.wisc.edu curTick(), m_pc); 1826899SN/A 1838190SLisa.Hsu@amd.com req->setThreadContext(index, 0); 1847053SN/A Packet::Command cmd; 1857053SN/A 1867053SN/A // 1 out of 8 chance, issue an atomic rather than a write 1877053SN/A // if ((random() & 0x7) == 0) { 1887053SN/A // cmd = MemCmd::SwapReq; 1897053SN/A // } else { 1906899SN/A cmd = MemCmd::WriteReq; 1917053SN/A // } 1926899SN/A 1938949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, cmd); 19410566Sandreas.hansson@arm.com uint8_t *writeData = new uint8_t[1]; 1957053SN/A *writeData = m_value + m_store_count; 1967053SN/A pkt->dataDynamic(writeData); 1976899SN/A 19811266SBrad.Beckmann@amd.com DPRINTF(RubyTest, "Seq write: index %d data 0x%x check 0x%x\n", index, 19910563Sandreas.hansson@arm.com *(pkt->getConstPtr<uint8_t>()), *writeData); 2006899SN/A 2017053SN/A // push the subblock onto the sender state. The sequencer will 2027053SN/A // update the subblock on the return 2039542Sandreas.hansson@arm.com pkt->senderState = new SenderState(writeAddr, req->getSize()); 2046899SN/A 2058975Sandreas.hansson@arm.com if (port->sendTimingReq(pkt)) { 2067053SN/A DPRINTF(RubyTest, "initiating action - successful\n"); 2077053SN/A DPRINTF(RubyTest, "status before action update: %s\n", 2087053SN/A (TesterStatus_to_string(m_status)).c_str()); 2097053SN/A m_status = TesterStatus_Action_Pending; 21011266SBrad.Beckmann@amd.com DPRINTF(RubyTest, "Check %s, State=Action_Pending\n", m_address); 2117053SN/A } else { 2127053SN/A // If the packet did not issue, must delete 2137053SN/A // Note: No need to delete the data, the packet destructor 2147053SN/A // will delete it 2159542Sandreas.hansson@arm.com delete pkt->senderState; 2167053SN/A delete pkt->req; 2177053SN/A delete pkt; 2187053SN/A 2197053SN/A DPRINTF(RubyTest, "failed to initiate action - sequencer not ready\n"); 2207053SN/A } 2217053SN/A 2227053SN/A DPRINTF(RubyTest, "status after action update: %s\n", 2236899SN/A (TesterStatus_to_string(m_status)).c_str()); 2246899SN/A} 2256899SN/A 2267053SN/Avoid 2277053SN/ACheck::initiateCheck() 2286899SN/A{ 2297053SN/A DPRINTF(RubyTest, "Initiating Check\n"); 2307053SN/A assert(m_status == TesterStatus_Ready); 2316899SN/A 23210348Sandreas.hansson@arm.com int index = random_mt.random(0, m_num_readers - 1); 2338950Sandreas.hansson@arm.com MasterPort* port = m_tester_ptr->getReadableCpuPort(index); 2346899SN/A 2357053SN/A Request::Flags flags; 2366899SN/A 2378932SBrad.Beckmann@amd.com // If necessary, make the request an instruction fetch 23811266SBrad.Beckmann@amd.com if (m_tester_ptr->isInstOnlyCpuPort(index) || 23911266SBrad.Beckmann@amd.com (m_tester_ptr->isInstDataCpuPort(index) && 24011266SBrad.Beckmann@amd.com (random_mt.random(0, 0x1)))) { 2417053SN/A flags.set(Request::INST_FETCH); 2427053SN/A } 2436899SN/A 2447568SN/A // Checks are sized depending on the number of bytes written 24511025Snilay@cs.wisc.edu Request *req = new Request(m_address, CHECK_SIZE, flags, 24611025Snilay@cs.wisc.edu m_tester_ptr->masterId(), curTick(), m_pc); 2477568SN/A 2488190SLisa.Hsu@amd.com req->setThreadContext(index, 0); 2498949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 2509208Snilay@cs.wisc.edu uint8_t *dataArray = new uint8_t[CHECK_SIZE]; 25110566Sandreas.hansson@arm.com pkt->dataDynamic(dataArray); 2526899SN/A 25311266SBrad.Beckmann@amd.com DPRINTF(RubyTest, "Seq read: index %d\n", index); 25411266SBrad.Beckmann@amd.com 2557053SN/A // push the subblock onto the sender state. The sequencer will 2567053SN/A // update the subblock on the return 2579542Sandreas.hansson@arm.com pkt->senderState = new SenderState(m_address, req->getSize()); 2586899SN/A 2598975Sandreas.hansson@arm.com if (port->sendTimingReq(pkt)) { 2607053SN/A DPRINTF(RubyTest, "initiating check - successful\n"); 2617053SN/A DPRINTF(RubyTest, "status before check update: %s\n", 2627053SN/A TesterStatus_to_string(m_status).c_str()); 2637053SN/A m_status = TesterStatus_Check_Pending; 26411266SBrad.Beckmann@amd.com DPRINTF(RubyTest, "Check %s, State=Check_Pending\n", m_address); 2657053SN/A } else { 2667053SN/A // If the packet did not issue, must delete 2677053SN/A // Note: No need to delete the data, the packet destructor 2687053SN/A // will delete it 2699542Sandreas.hansson@arm.com delete pkt->senderState; 2707053SN/A delete pkt->req; 2717053SN/A delete pkt; 2726899SN/A 2737053SN/A DPRINTF(RubyTest, "failed to initiate check - cpu port not ready\n"); 2747053SN/A } 2757053SN/A 2767053SN/A DPRINTF(RubyTest, "status after check update: %s\n", 2777053SN/A TesterStatus_to_string(m_status).c_str()); 2786899SN/A} 2796899SN/A 2807053SN/Avoid 28110302Snilay@cs.wisc.eduCheck::performCallback(NodeID proc, SubBlock* data, Cycles curTime) 2826899SN/A{ 28311025Snilay@cs.wisc.edu Addr address = data->getAddress(); 2846899SN/A 2857053SN/A // This isn't exactly right since we now have multi-byte checks 2867053SN/A // assert(getAddress() == address); 2876899SN/A 28811025Snilay@cs.wisc.edu assert(makeLineAddress(m_address) == makeLineAddress(address)); 2897053SN/A assert(data != NULL); 2907053SN/A 2917053SN/A DPRINTF(RubyTest, "RubyTester Callback\n"); 2926899SN/A debugPrint(); 2936899SN/A 2947053SN/A if (m_status == TesterStatus_Action_Pending) { 2957053SN/A DPRINTF(RubyTest, "Action callback write value: %d, currently %d\n", 2967053SN/A (m_value + m_store_count), data->getByte(0)); 2977053SN/A // Perform store one byte at a time 2987053SN/A data->setByte(0, (m_value + m_store_count)); 2997053SN/A m_store_count++; 3007053SN/A if (m_store_count == CHECK_SIZE) { 3017053SN/A m_status = TesterStatus_Ready; 30211266SBrad.Beckmann@amd.com DPRINTF(RubyTest, "Check %s, State=Ready\n", m_address); 3037053SN/A } else { 3047053SN/A m_status = TesterStatus_Idle; 30511266SBrad.Beckmann@amd.com DPRINTF(RubyTest, "Check %s, State=Idle store_count: %d\n", 30611266SBrad.Beckmann@amd.com m_address, m_store_count); 3077053SN/A } 3087053SN/A DPRINTF(RubyTest, "Action callback return data now %d\n", 3097053SN/A data->getByte(0)); 3107053SN/A } else if (m_status == TesterStatus_Check_Pending) { 3117053SN/A DPRINTF(RubyTest, "Check callback\n"); 3127053SN/A // Perform load/check 3137053SN/A for (int byte_number=0; byte_number<CHECK_SIZE; byte_number++) { 3149208Snilay@cs.wisc.edu if (uint8_t(m_value + byte_number) != data->getByte(byte_number)) { 3157805Snilay@cs.wisc.edu panic("Action/check failure: proc: %d address: %s data: %s " 3167805Snilay@cs.wisc.edu "byte_number: %d m_value+byte_number: %d byte: %d %s" 3177805Snilay@cs.wisc.edu "Time: %d\n", 3187805Snilay@cs.wisc.edu proc, address, data, byte_number, 3197805Snilay@cs.wisc.edu (int)m_value + byte_number, 3209475Snilay@cs.wisc.edu (int)data->getByte(byte_number), *this, curTime); 3217053SN/A } 3227053SN/A } 3237053SN/A DPRINTF(RubyTest, "Action/check success\n"); 3247053SN/A debugPrint(); 3256899SN/A 3267053SN/A // successful check complete, increment complete 3277053SN/A m_tester_ptr->incrementCheckCompletions(); 3286899SN/A 3297053SN/A m_status = TesterStatus_Idle; 33011266SBrad.Beckmann@amd.com DPRINTF(RubyTest, "Check %s, State=Idle\n", m_address); 3317053SN/A pickValue(); 3327053SN/A 3337053SN/A } else { 3347805Snilay@cs.wisc.edu panic("Unexpected TesterStatus: %s proc: %d data: %s m_status: %s " 3359475Snilay@cs.wisc.edu "time: %d\n", *this, proc, data, m_status, curTime); 3367053SN/A } 3377053SN/A 3387053SN/A DPRINTF(RubyTest, "proc: %d, Address: 0x%x\n", proc, 33911025Snilay@cs.wisc.edu makeLineAddress(m_address)); 3407053SN/A DPRINTF(RubyTest, "Callback done\n"); 3417053SN/A debugPrint(); 3426899SN/A} 3436899SN/A 3447053SN/Avoid 34511025Snilay@cs.wisc.eduCheck::changeAddress(Addr address) 3466899SN/A{ 3477053SN/A assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready); 3487053SN/A m_status = TesterStatus_Idle; 3497053SN/A m_address = address; 35011266SBrad.Beckmann@amd.com DPRINTF(RubyTest, "Check %s, State=Idle\n", m_address); 3517053SN/A m_store_count = 0; 3526899SN/A} 3536899SN/A 3547053SN/Avoid 3557053SN/ACheck::pickValue() 3566899SN/A{ 3577053SN/A assert(m_status == TesterStatus_Idle); 35810348Sandreas.hansson@arm.com m_value = random_mt.random(0, 0xff); // One byte 3597053SN/A m_store_count = 0; 3606899SN/A} 3616899SN/A 3627053SN/Avoid 3637053SN/ACheck::pickInitiatingNode() 3646899SN/A{ 3657053SN/A assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready); 3667053SN/A m_status = TesterStatus_Idle; 36710348Sandreas.hansson@arm.com m_initiatingNode = (random_mt.random(0, m_num_writers - 1)); 36811266SBrad.Beckmann@amd.com DPRINTF(RubyTest, "Check %s, State=Idle, picked initiating node %d\n", 36911266SBrad.Beckmann@amd.com m_address, m_initiatingNode); 3707053SN/A m_store_count = 0; 3716899SN/A} 3726899SN/A 3737053SN/Avoid 3747055SN/ACheck::print(std::ostream& out) const 3756899SN/A{ 3767053SN/A out << "[" 3777053SN/A << m_address << ", value: " 3787053SN/A << (int)m_value << ", status: " 3797053SN/A << m_status << ", initiating node: " 3807053SN/A << m_initiatingNode << ", store_count: " 3817053SN/A << m_store_count 3827055SN/A << "]" << std::flush; 3836899SN/A} 3846899SN/A 3857053SN/Avoid 3867053SN/ACheck::debugPrint() 3876899SN/A{ 3887053SN/A DPRINTF(RubyTest, 3897053SN/A "[%#x, value: %d, status: %s, initiating node: %d, store_count: %d]\n", 39011025Snilay@cs.wisc.edu m_address, (int)m_value, TesterStatus_to_string(m_status).c_str(), 3917053SN/A m_initiatingNode, m_store_count); 3926899SN/A} 393