Check.cc revision 11025
16899SN/A/*
26899SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
36899SN/A * Copyright (c) 2009 Advanced Micro Devices, Inc.
46899SN/A * All rights reserved.
56899SN/A *
66899SN/A * Redistribution and use in source and binary forms, with or without
76899SN/A * modification, are permitted provided that the following conditions are
86899SN/A * met: redistributions of source code must retain the above copyright
96899SN/A * notice, this list of conditions and the following disclaimer;
106899SN/A * redistributions in binary form must reproduce the above copyright
116899SN/A * notice, this list of conditions and the following disclaimer in the
126899SN/A * documentation and/or other materials provided with the distribution;
136899SN/A * neither the name of the copyright holders nor the names of its
146899SN/A * contributors may be used to endorse or promote products derived from
156899SN/A * this software without specific prior written permission.
166899SN/A *
176899SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
186899SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
196899SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
206899SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
216899SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
226899SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
236899SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
246899SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
256899SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
266899SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
276899SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
286899SN/A */
296899SN/A
3010348Sandreas.hansson@arm.com#include "base/random.hh"
317632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/Check.hh"
328232Snate@binkert.org#include "debug/RubyTest.hh"
337053SN/A#include "mem/ruby/common/SubBlock.hh"
346899SN/A
357053SN/Atypedef RubyTester::SenderState SenderState;
367053SN/A
3711025Snilay@cs.wisc.eduCheck::Check(Addr address, Addr pc, int _num_writers, int _num_readers,
3811025Snilay@cs.wisc.edu             RubyTester* _tester)
398932SBrad.Beckmann@amd.com    : m_num_writers(_num_writers), m_num_readers(_num_readers),
408932SBrad.Beckmann@amd.com      m_tester_ptr(_tester)
416899SN/A{
427053SN/A    m_status = TesterStatus_Idle;
436899SN/A
447053SN/A    pickValue();
457053SN/A    pickInitiatingNode();
467053SN/A    changeAddress(address);
477053SN/A    m_pc = pc;
4810348Sandreas.hansson@arm.com    m_access_mode = RubyAccessMode(random_mt.random(0,
4910348Sandreas.hansson@arm.com                                                    RubyAccessMode_NUM - 1));
507053SN/A    m_store_count = 0;
516899SN/A}
526899SN/A
537053SN/Avoid
547053SN/ACheck::initiate()
556899SN/A{
567053SN/A    DPRINTF(RubyTest, "initiating\n");
577053SN/A    debugPrint();
586899SN/A
597053SN/A    // currently no protocols support prefetches
6010348Sandreas.hansson@arm.com    if (false && (random_mt.random(0, 0xf) == 0)) {
617053SN/A        initiatePrefetch(); // Prefetch from random processor
627053SN/A    }
636899SN/A
6410348Sandreas.hansson@arm.com        if (m_tester_ptr->getCheckFlush() && (random_mt.random(0, 0xff) == 0)) {
658184Ssomayeh@cs.wisc.edu        initiateFlush(); // issue a Flush request from random processor
668184Ssomayeh@cs.wisc.edu    }
678184Ssomayeh@cs.wisc.edu
687053SN/A    if (m_status == TesterStatus_Idle) {
697053SN/A        initiateAction();
707053SN/A    } else if (m_status == TesterStatus_Ready) {
717053SN/A        initiateCheck();
727053SN/A    } else {
737053SN/A        // Pending - do nothing
747053SN/A        DPRINTF(RubyTest,
757053SN/A                "initiating action/check - failed: action/check is pending\n");
767053SN/A    }
776899SN/A}
786899SN/A
797053SN/Avoid
807053SN/ACheck::initiatePrefetch()
816899SN/A{
827053SN/A    DPRINTF(RubyTest, "initiating prefetch\n");
836899SN/A
8410348Sandreas.hansson@arm.com    int index = random_mt.random(0, m_num_readers - 1);
858950Sandreas.hansson@arm.com    MasterPort* port = m_tester_ptr->getReadableCpuPort(index);
866899SN/A
877053SN/A    Request::Flags flags;
887053SN/A    flags.set(Request::PREFETCH);
896899SN/A
907053SN/A    Packet::Command cmd;
916899SN/A
927053SN/A    // 1 in 8 chance this will be an exclusive prefetch
9310348Sandreas.hansson@arm.com    if (random_mt.random(0, 0x7) != 0) {
947053SN/A        cmd = MemCmd::ReadReq;
957053SN/A
968932SBrad.Beckmann@amd.com        // if necessary, make the request an instruction fetch
978950Sandreas.hansson@arm.com        if (m_tester_ptr->isInstReadableCpuPort(index)) {
987053SN/A            flags.set(Request::INST_FETCH);
997053SN/A        }
1007053SN/A    } else {
1017053SN/A        cmd = MemCmd::WriteReq;
1027053SN/A        flags.set(Request::PF_EXCLUSIVE);
1036899SN/A    }
1046899SN/A
1057568SN/A    // Prefetches are assumed to be 0 sized
10611025Snilay@cs.wisc.edu    Request *req = new Request(m_address, 0, flags,
10711025Snilay@cs.wisc.edu            m_tester_ptr->masterId(), curTick(), m_pc);
1088190SLisa.Hsu@amd.com    req->setThreadContext(index, 0);
1097568SN/A
1108949Sandreas.hansson@arm.com    PacketPtr pkt = new Packet(req, cmd);
11110562Sandreas.hansson@arm.com    // despite the oddity of the 0 size (questionable if this should
11210562Sandreas.hansson@arm.com    // even be allowed), a prefetch is still a read and as such needs
11310562Sandreas.hansson@arm.com    // a place to store the result
11410566Sandreas.hansson@arm.com    uint8_t *data = new uint8_t[1];
11510562Sandreas.hansson@arm.com    pkt->dataDynamic(data);
1166899SN/A
1177053SN/A    // push the subblock onto the sender state.  The sequencer will
1187053SN/A    // update the subblock on the return
1199542Sandreas.hansson@arm.com    pkt->senderState = new SenderState(m_address, req->getSize());
1206899SN/A
1218975Sandreas.hansson@arm.com    if (port->sendTimingReq(pkt)) {
1227053SN/A        DPRINTF(RubyTest, "successfully initiated prefetch.\n");
1237053SN/A    } else {
1247053SN/A        // If the packet did not issue, must delete
1259542Sandreas.hansson@arm.com        delete pkt->senderState;
1267053SN/A        delete pkt->req;
1277053SN/A        delete pkt;
1286899SN/A
1297053SN/A        DPRINTF(RubyTest,
1307053SN/A                "prefetch initiation failed because Port was busy.\n");
1317053SN/A    }
1326899SN/A}
1336899SN/A
1347053SN/Avoid
1358184Ssomayeh@cs.wisc.eduCheck::initiateFlush()
1368184Ssomayeh@cs.wisc.edu{
1378184Ssomayeh@cs.wisc.edu
1388184Ssomayeh@cs.wisc.edu    DPRINTF(RubyTest, "initiating Flush\n");
1398184Ssomayeh@cs.wisc.edu
14010348Sandreas.hansson@arm.com    int index = random_mt.random(0, m_num_writers - 1);
1418950Sandreas.hansson@arm.com    MasterPort* port = m_tester_ptr->getWritableCpuPort(index);
1428184Ssomayeh@cs.wisc.edu
1438184Ssomayeh@cs.wisc.edu    Request::Flags flags;
1448184Ssomayeh@cs.wisc.edu
14511025Snilay@cs.wisc.edu    Request *req = new Request(m_address, CHECK_SIZE, flags,
14611025Snilay@cs.wisc.edu            m_tester_ptr->masterId(), curTick(), m_pc);
1478184Ssomayeh@cs.wisc.edu
1488184Ssomayeh@cs.wisc.edu    Packet::Command cmd;
1498184Ssomayeh@cs.wisc.edu
1508184Ssomayeh@cs.wisc.edu    cmd = MemCmd::FlushReq;
1518184Ssomayeh@cs.wisc.edu
1528949Sandreas.hansson@arm.com    PacketPtr pkt = new Packet(req, cmd);
1538184Ssomayeh@cs.wisc.edu
1548184Ssomayeh@cs.wisc.edu    // push the subblock onto the sender state.  The sequencer will
1558184Ssomayeh@cs.wisc.edu    // update the subblock on the return
1569542Sandreas.hansson@arm.com    pkt->senderState = new SenderState(m_address, req->getSize());
1578184Ssomayeh@cs.wisc.edu
1588975Sandreas.hansson@arm.com    if (port->sendTimingReq(pkt)) {
1598184Ssomayeh@cs.wisc.edu        DPRINTF(RubyTest, "initiating Flush - successful\n");
1608184Ssomayeh@cs.wisc.edu    }
1618184Ssomayeh@cs.wisc.edu}
1628184Ssomayeh@cs.wisc.edu
1638184Ssomayeh@cs.wisc.eduvoid
1647053SN/ACheck::initiateAction()
1656899SN/A{
1667053SN/A    DPRINTF(RubyTest, "initiating Action\n");
1677053SN/A    assert(m_status == TesterStatus_Idle);
1686899SN/A
16910348Sandreas.hansson@arm.com    int index = random_mt.random(0, m_num_writers - 1);
1708950Sandreas.hansson@arm.com    MasterPort* port = m_tester_ptr->getWritableCpuPort(index);
1716899SN/A
1727053SN/A    Request::Flags flags;
1736899SN/A
1747053SN/A    // Create the particular address for the next byte to be written
17511025Snilay@cs.wisc.edu    Addr writeAddr(m_address + m_store_count);
1766899SN/A
1777053SN/A    // Stores are assumed to be 1 byte-sized
17811025Snilay@cs.wisc.edu    Request *req = new Request(writeAddr, 1, flags, m_tester_ptr->masterId(),
17911025Snilay@cs.wisc.edu                               curTick(), m_pc);
1806899SN/A
1818190SLisa.Hsu@amd.com    req->setThreadContext(index, 0);
1827053SN/A    Packet::Command cmd;
1837053SN/A
1847053SN/A    // 1 out of 8 chance, issue an atomic rather than a write
1857053SN/A    // if ((random() & 0x7) == 0) {
1867053SN/A    //     cmd = MemCmd::SwapReq;
1877053SN/A    // } else {
1886899SN/A    cmd = MemCmd::WriteReq;
1897053SN/A    // }
1906899SN/A
1918949Sandreas.hansson@arm.com    PacketPtr pkt = new Packet(req, cmd);
19210566Sandreas.hansson@arm.com    uint8_t *writeData = new uint8_t[1];
1937053SN/A    *writeData = m_value + m_store_count;
1947053SN/A    pkt->dataDynamic(writeData);
1956899SN/A
1967053SN/A    DPRINTF(RubyTest, "data 0x%x check 0x%x\n",
19710563Sandreas.hansson@arm.com            *(pkt->getConstPtr<uint8_t>()), *writeData);
1986899SN/A
1997053SN/A    // push the subblock onto the sender state.  The sequencer will
2007053SN/A    // update the subblock on the return
2019542Sandreas.hansson@arm.com    pkt->senderState = new SenderState(writeAddr, req->getSize());
2026899SN/A
2038975Sandreas.hansson@arm.com    if (port->sendTimingReq(pkt)) {
2047053SN/A        DPRINTF(RubyTest, "initiating action - successful\n");
2057053SN/A        DPRINTF(RubyTest, "status before action update: %s\n",
2067053SN/A                (TesterStatus_to_string(m_status)).c_str());
2077053SN/A        m_status = TesterStatus_Action_Pending;
2087053SN/A    } else {
2097053SN/A        // If the packet did not issue, must delete
2107053SN/A        // Note: No need to delete the data, the packet destructor
2117053SN/A        // will delete it
2129542Sandreas.hansson@arm.com        delete pkt->senderState;
2137053SN/A        delete pkt->req;
2147053SN/A        delete pkt;
2157053SN/A
2167053SN/A        DPRINTF(RubyTest, "failed to initiate action - sequencer not ready\n");
2177053SN/A    }
2187053SN/A
2197053SN/A    DPRINTF(RubyTest, "status after action update: %s\n",
2206899SN/A            (TesterStatus_to_string(m_status)).c_str());
2216899SN/A}
2226899SN/A
2237053SN/Avoid
2247053SN/ACheck::initiateCheck()
2256899SN/A{
2267053SN/A    DPRINTF(RubyTest, "Initiating Check\n");
2277053SN/A    assert(m_status == TesterStatus_Ready);
2286899SN/A
22910348Sandreas.hansson@arm.com    int index = random_mt.random(0, m_num_readers - 1);
2308950Sandreas.hansson@arm.com    MasterPort* port = m_tester_ptr->getReadableCpuPort(index);
2316899SN/A
2327053SN/A    Request::Flags flags;
2336899SN/A
2348932SBrad.Beckmann@amd.com    // If necessary, make the request an instruction fetch
2358950Sandreas.hansson@arm.com    if (m_tester_ptr->isInstReadableCpuPort(index)) {
2367053SN/A        flags.set(Request::INST_FETCH);
2377053SN/A    }
2386899SN/A
2397568SN/A    // Checks are sized depending on the number of bytes written
24011025Snilay@cs.wisc.edu    Request *req = new Request(m_address, CHECK_SIZE, flags,
24111025Snilay@cs.wisc.edu                               m_tester_ptr->masterId(), curTick(), m_pc);
2427568SN/A
2438190SLisa.Hsu@amd.com    req->setThreadContext(index, 0);
2448949Sandreas.hansson@arm.com    PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
2459208Snilay@cs.wisc.edu    uint8_t *dataArray = new uint8_t[CHECK_SIZE];
24610566Sandreas.hansson@arm.com    pkt->dataDynamic(dataArray);
2476899SN/A
2487053SN/A    // push the subblock onto the sender state.  The sequencer will
2497053SN/A    // update the subblock on the return
2509542Sandreas.hansson@arm.com    pkt->senderState = new SenderState(m_address, req->getSize());
2516899SN/A
2528975Sandreas.hansson@arm.com    if (port->sendTimingReq(pkt)) {
2537053SN/A        DPRINTF(RubyTest, "initiating check - successful\n");
2547053SN/A        DPRINTF(RubyTest, "status before check update: %s\n",
2557053SN/A                TesterStatus_to_string(m_status).c_str());
2567053SN/A        m_status = TesterStatus_Check_Pending;
2577053SN/A    } else {
2587053SN/A        // If the packet did not issue, must delete
2597053SN/A        // Note: No need to delete the data, the packet destructor
2607053SN/A        // will delete it
2619542Sandreas.hansson@arm.com        delete pkt->senderState;
2627053SN/A        delete pkt->req;
2637053SN/A        delete pkt;
2646899SN/A
2657053SN/A        DPRINTF(RubyTest, "failed to initiate check - cpu port not ready\n");
2667053SN/A    }
2677053SN/A
2687053SN/A    DPRINTF(RubyTest, "status after check update: %s\n",
2697053SN/A            TesterStatus_to_string(m_status).c_str());
2706899SN/A}
2716899SN/A
2727053SN/Avoid
27310302Snilay@cs.wisc.eduCheck::performCallback(NodeID proc, SubBlock* data, Cycles curTime)
2746899SN/A{
27511025Snilay@cs.wisc.edu    Addr address = data->getAddress();
2766899SN/A
2777053SN/A    // This isn't exactly right since we now have multi-byte checks
2787053SN/A    //  assert(getAddress() == address);
2796899SN/A
28011025Snilay@cs.wisc.edu    assert(makeLineAddress(m_address) == makeLineAddress(address));
2817053SN/A    assert(data != NULL);
2827053SN/A
2837053SN/A    DPRINTF(RubyTest, "RubyTester Callback\n");
2846899SN/A    debugPrint();
2856899SN/A
2867053SN/A    if (m_status == TesterStatus_Action_Pending) {
2877053SN/A        DPRINTF(RubyTest, "Action callback write value: %d, currently %d\n",
2887053SN/A                (m_value + m_store_count), data->getByte(0));
2897053SN/A        // Perform store one byte at a time
2907053SN/A        data->setByte(0, (m_value + m_store_count));
2917053SN/A        m_store_count++;
2927053SN/A        if (m_store_count == CHECK_SIZE) {
2937053SN/A            m_status = TesterStatus_Ready;
2947053SN/A        } else {
2957053SN/A            m_status = TesterStatus_Idle;
2967053SN/A        }
2977053SN/A        DPRINTF(RubyTest, "Action callback return data now %d\n",
2987053SN/A                data->getByte(0));
2997053SN/A    } else if (m_status == TesterStatus_Check_Pending) {
3007053SN/A        DPRINTF(RubyTest, "Check callback\n");
3017053SN/A        // Perform load/check
3027053SN/A        for (int byte_number=0; byte_number<CHECK_SIZE; byte_number++) {
3039208Snilay@cs.wisc.edu            if (uint8_t(m_value + byte_number) != data->getByte(byte_number)) {
3047805Snilay@cs.wisc.edu                panic("Action/check failure: proc: %d address: %s data: %s "
3057805Snilay@cs.wisc.edu                      "byte_number: %d m_value+byte_number: %d byte: %d %s"
3067805Snilay@cs.wisc.edu                      "Time: %d\n",
3077805Snilay@cs.wisc.edu                      proc, address, data, byte_number,
3087805Snilay@cs.wisc.edu                      (int)m_value + byte_number,
3099475Snilay@cs.wisc.edu                      (int)data->getByte(byte_number), *this, curTime);
3107053SN/A            }
3117053SN/A        }
3127053SN/A        DPRINTF(RubyTest, "Action/check success\n");
3137053SN/A        debugPrint();
3146899SN/A
3157053SN/A        // successful check complete, increment complete
3167053SN/A        m_tester_ptr->incrementCheckCompletions();
3176899SN/A
3187053SN/A        m_status = TesterStatus_Idle;
3197053SN/A        pickValue();
3207053SN/A
3217053SN/A    } else {
3227805Snilay@cs.wisc.edu        panic("Unexpected TesterStatus: %s proc: %d data: %s m_status: %s "
3239475Snilay@cs.wisc.edu              "time: %d\n", *this, proc, data, m_status, curTime);
3247053SN/A    }
3257053SN/A
3267053SN/A    DPRINTF(RubyTest, "proc: %d, Address: 0x%x\n", proc,
32711025Snilay@cs.wisc.edu            makeLineAddress(m_address));
3287053SN/A    DPRINTF(RubyTest, "Callback done\n");
3297053SN/A    debugPrint();
3306899SN/A}
3316899SN/A
3327053SN/Avoid
33311025Snilay@cs.wisc.eduCheck::changeAddress(Addr address)
3346899SN/A{
3357053SN/A    assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready);
3367053SN/A    m_status = TesterStatus_Idle;
3377053SN/A    m_address = address;
3387053SN/A    m_store_count = 0;
3396899SN/A}
3406899SN/A
3417053SN/Avoid
3427053SN/ACheck::pickValue()
3436899SN/A{
3447053SN/A    assert(m_status == TesterStatus_Idle);
3457053SN/A    m_status = TesterStatus_Idle;
34610348Sandreas.hansson@arm.com    m_value = random_mt.random(0, 0xff); // One byte
3477053SN/A    m_store_count = 0;
3486899SN/A}
3496899SN/A
3507053SN/Avoid
3517053SN/ACheck::pickInitiatingNode()
3526899SN/A{
3537053SN/A    assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready);
3547053SN/A    m_status = TesterStatus_Idle;
35510348Sandreas.hansson@arm.com    m_initiatingNode = (random_mt.random(0, m_num_writers - 1));
3567053SN/A    DPRINTF(RubyTest, "picked initiating node %d\n", m_initiatingNode);
3577053SN/A    m_store_count = 0;
3586899SN/A}
3596899SN/A
3607053SN/Avoid
3617055SN/ACheck::print(std::ostream& out) const
3626899SN/A{
3637053SN/A    out << "["
3647053SN/A        << m_address << ", value: "
3657053SN/A        << (int)m_value << ", status: "
3667053SN/A        << m_status << ", initiating node: "
3677053SN/A        << m_initiatingNode << ", store_count: "
3687053SN/A        << m_store_count
3697055SN/A        << "]" << std::flush;
3706899SN/A}
3716899SN/A
3727053SN/Avoid
3737053SN/ACheck::debugPrint()
3746899SN/A{
3757053SN/A    DPRINTF(RubyTest,
3767053SN/A        "[%#x, value: %d, status: %s, initiating node: %d, store_count: %d]\n",
37711025Snilay@cs.wisc.edu        m_address, (int)m_value, TesterStatus_to_string(m_status).c_str(),
3787053SN/A        m_initiatingNode, m_store_count);
3796899SN/A}
380