Check.cc revision 10563
16899SN/A/* 26899SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 36899SN/A * Copyright (c) 2009 Advanced Micro Devices, Inc. 46899SN/A * All rights reserved. 56899SN/A * 66899SN/A * Redistribution and use in source and binary forms, with or without 76899SN/A * modification, are permitted provided that the following conditions are 86899SN/A * met: redistributions of source code must retain the above copyright 96899SN/A * notice, this list of conditions and the following disclaimer; 106899SN/A * redistributions in binary form must reproduce the above copyright 116899SN/A * notice, this list of conditions and the following disclaimer in the 126899SN/A * documentation and/or other materials provided with the distribution; 136899SN/A * neither the name of the copyright holders nor the names of its 146899SN/A * contributors may be used to endorse or promote products derived from 156899SN/A * this software without specific prior written permission. 166899SN/A * 176899SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186899SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196899SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206899SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216899SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226899SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236899SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246899SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256899SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266899SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276899SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286899SN/A */ 296899SN/A 3010348Sandreas.hansson@arm.com#include "base/random.hh" 317632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/Check.hh" 328232Snate@binkert.org#include "debug/RubyTest.hh" 337053SN/A#include "mem/ruby/common/SubBlock.hh" 346899SN/A#include "mem/ruby/system/Sequencer.hh" 356899SN/A#include "mem/ruby/system/System.hh" 366899SN/A 377053SN/Atypedef RubyTester::SenderState SenderState; 387053SN/A 397053SN/ACheck::Check(const Address& address, const Address& pc, 408932SBrad.Beckmann@amd.com int _num_writers, int _num_readers, RubyTester* _tester) 418932SBrad.Beckmann@amd.com : m_num_writers(_num_writers), m_num_readers(_num_readers), 428932SBrad.Beckmann@amd.com m_tester_ptr(_tester) 436899SN/A{ 447053SN/A m_status = TesterStatus_Idle; 456899SN/A 467053SN/A pickValue(); 477053SN/A pickInitiatingNode(); 487053SN/A changeAddress(address); 497053SN/A m_pc = pc; 5010348Sandreas.hansson@arm.com m_access_mode = RubyAccessMode(random_mt.random(0, 5110348Sandreas.hansson@arm.com RubyAccessMode_NUM - 1)); 527053SN/A m_store_count = 0; 536899SN/A} 546899SN/A 557053SN/Avoid 567053SN/ACheck::initiate() 576899SN/A{ 587053SN/A DPRINTF(RubyTest, "initiating\n"); 597053SN/A debugPrint(); 606899SN/A 617053SN/A // currently no protocols support prefetches 6210348Sandreas.hansson@arm.com if (false && (random_mt.random(0, 0xf) == 0)) { 637053SN/A initiatePrefetch(); // Prefetch from random processor 647053SN/A } 656899SN/A 6610348Sandreas.hansson@arm.com if (m_tester_ptr->getCheckFlush() && (random_mt.random(0, 0xff) == 0)) { 678184Ssomayeh@cs.wisc.edu initiateFlush(); // issue a Flush request from random processor 688184Ssomayeh@cs.wisc.edu } 698184Ssomayeh@cs.wisc.edu 707053SN/A if (m_status == TesterStatus_Idle) { 717053SN/A initiateAction(); 727053SN/A } else if (m_status == TesterStatus_Ready) { 737053SN/A initiateCheck(); 747053SN/A } else { 757053SN/A // Pending - do nothing 767053SN/A DPRINTF(RubyTest, 777053SN/A "initiating action/check - failed: action/check is pending\n"); 787053SN/A } 796899SN/A} 806899SN/A 817053SN/Avoid 827053SN/ACheck::initiatePrefetch() 836899SN/A{ 847053SN/A DPRINTF(RubyTest, "initiating prefetch\n"); 856899SN/A 8610348Sandreas.hansson@arm.com int index = random_mt.random(0, m_num_readers - 1); 878950Sandreas.hansson@arm.com MasterPort* port = m_tester_ptr->getReadableCpuPort(index); 886899SN/A 897053SN/A Request::Flags flags; 907053SN/A flags.set(Request::PREFETCH); 916899SN/A 927053SN/A Packet::Command cmd; 936899SN/A 947053SN/A // 1 in 8 chance this will be an exclusive prefetch 9510348Sandreas.hansson@arm.com if (random_mt.random(0, 0x7) != 0) { 967053SN/A cmd = MemCmd::ReadReq; 977053SN/A 988932SBrad.Beckmann@amd.com // if necessary, make the request an instruction fetch 998950Sandreas.hansson@arm.com if (m_tester_ptr->isInstReadableCpuPort(index)) { 1007053SN/A flags.set(Request::INST_FETCH); 1017053SN/A } 1027053SN/A } else { 1037053SN/A cmd = MemCmd::WriteReq; 1047053SN/A flags.set(Request::PF_EXCLUSIVE); 1056899SN/A } 1066899SN/A 1077568SN/A // Prefetches are assumed to be 0 sized 1088832SAli.Saidi@ARM.com Request *req = new Request(m_address.getAddress(), 0, flags, 1098832SAli.Saidi@ARM.com m_tester_ptr->masterId(), curTick(), m_pc.getAddress()); 1108190SLisa.Hsu@amd.com req->setThreadContext(index, 0); 1117568SN/A 1128949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, cmd); 11310562Sandreas.hansson@arm.com // despite the oddity of the 0 size (questionable if this should 11410562Sandreas.hansson@arm.com // even be allowed), a prefetch is still a read and as such needs 11510562Sandreas.hansson@arm.com // a place to store the result 11610562Sandreas.hansson@arm.com uint8_t *data = new uint8_t; 11710562Sandreas.hansson@arm.com pkt->dataDynamic(data); 1186899SN/A 1197053SN/A // push the subblock onto the sender state. The sequencer will 1207053SN/A // update the subblock on the return 1219542Sandreas.hansson@arm.com pkt->senderState = new SenderState(m_address, req->getSize()); 1226899SN/A 1238975Sandreas.hansson@arm.com if (port->sendTimingReq(pkt)) { 1247053SN/A DPRINTF(RubyTest, "successfully initiated prefetch.\n"); 1257053SN/A } else { 1267053SN/A // If the packet did not issue, must delete 1279542Sandreas.hansson@arm.com delete pkt->senderState; 1287053SN/A delete pkt->req; 1297053SN/A delete pkt; 1306899SN/A 1317053SN/A DPRINTF(RubyTest, 1327053SN/A "prefetch initiation failed because Port was busy.\n"); 1337053SN/A } 1346899SN/A} 1356899SN/A 1367053SN/Avoid 1378184Ssomayeh@cs.wisc.eduCheck::initiateFlush() 1388184Ssomayeh@cs.wisc.edu{ 1398184Ssomayeh@cs.wisc.edu 1408184Ssomayeh@cs.wisc.edu DPRINTF(RubyTest, "initiating Flush\n"); 1418184Ssomayeh@cs.wisc.edu 14210348Sandreas.hansson@arm.com int index = random_mt.random(0, m_num_writers - 1); 1438950Sandreas.hansson@arm.com MasterPort* port = m_tester_ptr->getWritableCpuPort(index); 1448184Ssomayeh@cs.wisc.edu 1458184Ssomayeh@cs.wisc.edu Request::Flags flags; 1468184Ssomayeh@cs.wisc.edu 1478832SAli.Saidi@ARM.com Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags, 1488832SAli.Saidi@ARM.com m_tester_ptr->masterId(), curTick(), m_pc.getAddress()); 1498184Ssomayeh@cs.wisc.edu 1508184Ssomayeh@cs.wisc.edu Packet::Command cmd; 1518184Ssomayeh@cs.wisc.edu 1528184Ssomayeh@cs.wisc.edu cmd = MemCmd::FlushReq; 1538184Ssomayeh@cs.wisc.edu 1548949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, cmd); 1558184Ssomayeh@cs.wisc.edu 1568184Ssomayeh@cs.wisc.edu // push the subblock onto the sender state. The sequencer will 1578184Ssomayeh@cs.wisc.edu // update the subblock on the return 1589542Sandreas.hansson@arm.com pkt->senderState = new SenderState(m_address, req->getSize()); 1598184Ssomayeh@cs.wisc.edu 1608975Sandreas.hansson@arm.com if (port->sendTimingReq(pkt)) { 1618184Ssomayeh@cs.wisc.edu DPRINTF(RubyTest, "initiating Flush - successful\n"); 1628184Ssomayeh@cs.wisc.edu } 1638184Ssomayeh@cs.wisc.edu} 1648184Ssomayeh@cs.wisc.edu 1658184Ssomayeh@cs.wisc.eduvoid 1667053SN/ACheck::initiateAction() 1676899SN/A{ 1687053SN/A DPRINTF(RubyTest, "initiating Action\n"); 1697053SN/A assert(m_status == TesterStatus_Idle); 1706899SN/A 17110348Sandreas.hansson@arm.com int index = random_mt.random(0, m_num_writers - 1); 1728950Sandreas.hansson@arm.com MasterPort* port = m_tester_ptr->getWritableCpuPort(index); 1736899SN/A 1747053SN/A Request::Flags flags; 1756899SN/A 1767053SN/A // Create the particular address for the next byte to be written 1777053SN/A Address writeAddr(m_address.getAddress() + m_store_count); 1786899SN/A 1797053SN/A // Stores are assumed to be 1 byte-sized 1808832SAli.Saidi@ARM.com Request *req = new Request(writeAddr.getAddress(), 1, flags, 1818832SAli.Saidi@ARM.com m_tester_ptr->masterId(), curTick(), 1827053SN/A m_pc.getAddress()); 1836899SN/A 1848190SLisa.Hsu@amd.com req->setThreadContext(index, 0); 1857053SN/A Packet::Command cmd; 1867053SN/A 1877053SN/A // 1 out of 8 chance, issue an atomic rather than a write 1887053SN/A // if ((random() & 0x7) == 0) { 1897053SN/A // cmd = MemCmd::SwapReq; 1907053SN/A // } else { 1916899SN/A cmd = MemCmd::WriteReq; 1927053SN/A // } 1936899SN/A 1948949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, cmd); 1959208Snilay@cs.wisc.edu uint8_t *writeData = new uint8_t; 1967053SN/A *writeData = m_value + m_store_count; 1977053SN/A pkt->dataDynamic(writeData); 1986899SN/A 1997053SN/A DPRINTF(RubyTest, "data 0x%x check 0x%x\n", 20010563Sandreas.hansson@arm.com *(pkt->getConstPtr<uint8_t>()), *writeData); 2016899SN/A 2027053SN/A // push the subblock onto the sender state. The sequencer will 2037053SN/A // update the subblock on the return 2049542Sandreas.hansson@arm.com pkt->senderState = new SenderState(writeAddr, req->getSize()); 2056899SN/A 2068975Sandreas.hansson@arm.com if (port->sendTimingReq(pkt)) { 2077053SN/A DPRINTF(RubyTest, "initiating action - successful\n"); 2087053SN/A DPRINTF(RubyTest, "status before action update: %s\n", 2097053SN/A (TesterStatus_to_string(m_status)).c_str()); 2107053SN/A m_status = TesterStatus_Action_Pending; 2117053SN/A } else { 2127053SN/A // If the packet did not issue, must delete 2137053SN/A // Note: No need to delete the data, the packet destructor 2147053SN/A // will delete it 2159542Sandreas.hansson@arm.com delete pkt->senderState; 2167053SN/A delete pkt->req; 2177053SN/A delete pkt; 2187053SN/A 2197053SN/A DPRINTF(RubyTest, "failed to initiate action - sequencer not ready\n"); 2207053SN/A } 2217053SN/A 2227053SN/A DPRINTF(RubyTest, "status after action update: %s\n", 2236899SN/A (TesterStatus_to_string(m_status)).c_str()); 2246899SN/A} 2256899SN/A 2267053SN/Avoid 2277053SN/ACheck::initiateCheck() 2286899SN/A{ 2297053SN/A DPRINTF(RubyTest, "Initiating Check\n"); 2307053SN/A assert(m_status == TesterStatus_Ready); 2316899SN/A 23210348Sandreas.hansson@arm.com int index = random_mt.random(0, m_num_readers - 1); 2338950Sandreas.hansson@arm.com MasterPort* port = m_tester_ptr->getReadableCpuPort(index); 2346899SN/A 2357053SN/A Request::Flags flags; 2366899SN/A 2378932SBrad.Beckmann@amd.com // If necessary, make the request an instruction fetch 2388950Sandreas.hansson@arm.com if (m_tester_ptr->isInstReadableCpuPort(index)) { 2397053SN/A flags.set(Request::INST_FETCH); 2407053SN/A } 2416899SN/A 2427568SN/A // Checks are sized depending on the number of bytes written 2437568SN/A Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags, 2448832SAli.Saidi@ARM.com m_tester_ptr->masterId(), curTick(), m_pc.getAddress()); 2457568SN/A 2468190SLisa.Hsu@amd.com req->setThreadContext(index, 0); 2478949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 2489208Snilay@cs.wisc.edu uint8_t *dataArray = new uint8_t[CHECK_SIZE]; 2497053SN/A pkt->dataDynamicArray(dataArray); 2506899SN/A 2517053SN/A // push the subblock onto the sender state. The sequencer will 2527053SN/A // update the subblock on the return 2539542Sandreas.hansson@arm.com pkt->senderState = new SenderState(m_address, req->getSize()); 2546899SN/A 2558975Sandreas.hansson@arm.com if (port->sendTimingReq(pkt)) { 2567053SN/A DPRINTF(RubyTest, "initiating check - successful\n"); 2577053SN/A DPRINTF(RubyTest, "status before check update: %s\n", 2587053SN/A TesterStatus_to_string(m_status).c_str()); 2597053SN/A m_status = TesterStatus_Check_Pending; 2607053SN/A } else { 2617053SN/A // If the packet did not issue, must delete 2627053SN/A // Note: No need to delete the data, the packet destructor 2637053SN/A // will delete it 2649542Sandreas.hansson@arm.com delete pkt->senderState; 2657053SN/A delete pkt->req; 2667053SN/A delete pkt; 2676899SN/A 2687053SN/A DPRINTF(RubyTest, "failed to initiate check - cpu port not ready\n"); 2697053SN/A } 2707053SN/A 2717053SN/A DPRINTF(RubyTest, "status after check update: %s\n", 2727053SN/A TesterStatus_to_string(m_status).c_str()); 2736899SN/A} 2746899SN/A 2757053SN/Avoid 27610302Snilay@cs.wisc.eduCheck::performCallback(NodeID proc, SubBlock* data, Cycles curTime) 2776899SN/A{ 2787053SN/A Address address = data->getAddress(); 2796899SN/A 2807053SN/A // This isn't exactly right since we now have multi-byte checks 2817053SN/A // assert(getAddress() == address); 2826899SN/A 2837053SN/A assert(getAddress().getLineAddress() == address.getLineAddress()); 2847053SN/A assert(data != NULL); 2857053SN/A 2867053SN/A DPRINTF(RubyTest, "RubyTester Callback\n"); 2876899SN/A debugPrint(); 2886899SN/A 2897053SN/A if (m_status == TesterStatus_Action_Pending) { 2907053SN/A DPRINTF(RubyTest, "Action callback write value: %d, currently %d\n", 2917053SN/A (m_value + m_store_count), data->getByte(0)); 2927053SN/A // Perform store one byte at a time 2937053SN/A data->setByte(0, (m_value + m_store_count)); 2947053SN/A m_store_count++; 2957053SN/A if (m_store_count == CHECK_SIZE) { 2967053SN/A m_status = TesterStatus_Ready; 2977053SN/A } else { 2987053SN/A m_status = TesterStatus_Idle; 2997053SN/A } 3007053SN/A DPRINTF(RubyTest, "Action callback return data now %d\n", 3017053SN/A data->getByte(0)); 3027053SN/A } else if (m_status == TesterStatus_Check_Pending) { 3037053SN/A DPRINTF(RubyTest, "Check callback\n"); 3047053SN/A // Perform load/check 3057053SN/A for (int byte_number=0; byte_number<CHECK_SIZE; byte_number++) { 3069208Snilay@cs.wisc.edu if (uint8_t(m_value + byte_number) != data->getByte(byte_number)) { 3077805Snilay@cs.wisc.edu panic("Action/check failure: proc: %d address: %s data: %s " 3087805Snilay@cs.wisc.edu "byte_number: %d m_value+byte_number: %d byte: %d %s" 3097805Snilay@cs.wisc.edu "Time: %d\n", 3107805Snilay@cs.wisc.edu proc, address, data, byte_number, 3117805Snilay@cs.wisc.edu (int)m_value + byte_number, 3129475Snilay@cs.wisc.edu (int)data->getByte(byte_number), *this, curTime); 3137053SN/A } 3147053SN/A } 3157053SN/A DPRINTF(RubyTest, "Action/check success\n"); 3167053SN/A debugPrint(); 3176899SN/A 3187053SN/A // successful check complete, increment complete 3197053SN/A m_tester_ptr->incrementCheckCompletions(); 3206899SN/A 3217053SN/A m_status = TesterStatus_Idle; 3227053SN/A pickValue(); 3237053SN/A 3247053SN/A } else { 3257805Snilay@cs.wisc.edu panic("Unexpected TesterStatus: %s proc: %d data: %s m_status: %s " 3269475Snilay@cs.wisc.edu "time: %d\n", *this, proc, data, m_status, curTime); 3277053SN/A } 3287053SN/A 3297053SN/A DPRINTF(RubyTest, "proc: %d, Address: 0x%x\n", proc, 3307053SN/A getAddress().getLineAddress()); 3317053SN/A DPRINTF(RubyTest, "Callback done\n"); 3327053SN/A debugPrint(); 3336899SN/A} 3346899SN/A 3357053SN/Avoid 3367053SN/ACheck::changeAddress(const Address& address) 3376899SN/A{ 3387053SN/A assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready); 3397053SN/A m_status = TesterStatus_Idle; 3407053SN/A m_address = address; 3417053SN/A m_store_count = 0; 3426899SN/A} 3436899SN/A 3447053SN/Avoid 3457053SN/ACheck::pickValue() 3466899SN/A{ 3477053SN/A assert(m_status == TesterStatus_Idle); 3487053SN/A m_status = TesterStatus_Idle; 34910348Sandreas.hansson@arm.com m_value = random_mt.random(0, 0xff); // One byte 3507053SN/A m_store_count = 0; 3516899SN/A} 3526899SN/A 3537053SN/Avoid 3547053SN/ACheck::pickInitiatingNode() 3556899SN/A{ 3567053SN/A assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready); 3577053SN/A m_status = TesterStatus_Idle; 35810348Sandreas.hansson@arm.com m_initiatingNode = (random_mt.random(0, m_num_writers - 1)); 3597053SN/A DPRINTF(RubyTest, "picked initiating node %d\n", m_initiatingNode); 3607053SN/A m_store_count = 0; 3616899SN/A} 3626899SN/A 3637053SN/Avoid 3647055SN/ACheck::print(std::ostream& out) const 3656899SN/A{ 3667053SN/A out << "[" 3677053SN/A << m_address << ", value: " 3687053SN/A << (int)m_value << ", status: " 3697053SN/A << m_status << ", initiating node: " 3707053SN/A << m_initiatingNode << ", store_count: " 3717053SN/A << m_store_count 3727055SN/A << "]" << std::flush; 3736899SN/A} 3746899SN/A 3757053SN/Avoid 3767053SN/ACheck::debugPrint() 3776899SN/A{ 3787053SN/A DPRINTF(RubyTest, 3797053SN/A "[%#x, value: %d, status: %s, initiating node: %d, store_count: %d]\n", 3807053SN/A m_address.getAddress(), (int)m_value, 3817053SN/A TesterStatus_to_string(m_status).c_str(), 3827053SN/A m_initiatingNode, m_store_count); 3836899SN/A} 384