memtest.hh revision 9301:1e8d01c15a77
12292SN/A/* 28948Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 310239Sbinhpham@cs.rutgers.edu * All rights reserved. 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68707Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78707Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88707Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98707Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108707Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118707Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128707Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138707Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 148707Sandreas.hansson@arm.com * this software without specific prior written permission. 152727Sktlim@umich.edu * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272292SN/A * 282292SN/A * Authors: Erik Hallnor 292292SN/A * Steve Reinhardt 302292SN/A */ 312292SN/A 322292SN/A#ifndef __CPU_MEMTEST_MEMTEST_HH__ 332292SN/A#define __CPU_MEMTEST_MEMTEST_HH__ 342292SN/A 352292SN/A#include <set> 362292SN/A 372292SN/A#include "base/statistics.hh" 382292SN/A#include "mem/mem_object.hh" 392292SN/A#include "mem/port.hh" 402689Sktlim@umich.edu#include "mem/port_proxy.hh" 412689Sktlim@umich.edu#include "params/MemTest.hh" 422292SN/A#include "sim/eventq.hh" 432292SN/A#include "sim/sim_exit.hh" 449944Smatt.horsnell@ARM.com#include "sim/sim_object.hh" 459944Smatt.horsnell@ARM.com#include "sim/stats.hh" 469944Smatt.horsnell@ARM.com 472329SN/Aclass Packet; 482980Sgblack@eecs.umich.educlass MemTest : public MemObject 492329SN/A{ 502329SN/A public: 512292SN/A typedef MemTestParams Params; 529444SAndreas.Sandberg@ARM.com MemTest(const Params *p); 538232Snate@binkert.org 548232Snate@binkert.org virtual void init(); 558232Snate@binkert.org 566221Snate@binkert.org // register statistics 572292SN/A virtual void regStats(); 586221Snate@binkert.org 595529Snate@binkert.org // main simulation loop (one cycle) 602292SN/A void tick(); 615529Snate@binkert.org 628707Sandreas.hansson@arm.com virtual BaseMasterPort &getMasterPort(const std::string &if_name, 634329Sktlim@umich.edu PortID idx = InvalidPortID); 644329Sktlim@umich.edu 655529Snate@binkert.org /** 662907Sktlim@umich.edu * Print state of address in memory system via PrintReq (for 672292SN/A * debugging). 689868Sjthestness@gmail.com */ 699868Sjthestness@gmail.com void printAddr(Addr a); 702292SN/A 712292SN/A protected: 722292SN/A class TickEvent : public Event 732980Sgblack@eecs.umich.edu { 742292SN/A private: 752292SN/A MemTest *cpu; 762292SN/A 772292SN/A public: 782292SN/A TickEvent(MemTest *c) : Event(CPU_Tick_Pri), cpu(c) {} 792292SN/A void process() { cpu->tick(); } 802292SN/A virtual const char *description() const { return "MemTest tick"; } 812292SN/A }; 822292SN/A 832292SN/A TickEvent tickEvent; 842292SN/A 854329Sktlim@umich.edu class CpuPort : public MasterPort 862292SN/A { 872292SN/A MemTest *memtest; 882292SN/A 892292SN/A public: 902292SN/A 912292SN/A CpuPort(const std::string &_name, MemTest *_memtest) 922292SN/A : MasterPort(_name, _memtest), memtest(_memtest) 934329Sktlim@umich.edu { } 942292SN/A 958346Sksewell@umich.edu protected: 962292SN/A 972292SN/A virtual bool recvTimingResp(PacketPtr pkt); 982292SN/A 992292SN/A virtual void recvTimingSnoopReq(PacketPtr pkt) { } 1002292SN/A 1012292SN/A virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; } 1022292SN/A 1032292SN/A virtual void recvFunctionalSnoop(PacketPtr pkt) { } 1042292SN/A 1052292SN/A virtual void recvRetry(); 1062292SN/A }; 1072292SN/A 1084329Sktlim@umich.edu CpuPort cachePort; 1092292SN/A CpuPort funcPort; 1108346Sksewell@umich.edu PortProxy funcProxy; 1112292SN/A 1122292SN/A class MemTestSenderState : public Packet::SenderState 1132292SN/A { 1142292SN/A public: 1152292SN/A /** Constructor. */ 1162292SN/A MemTestSenderState(uint8_t *_data) 1172292SN/A : data(_data) 1189868Sjthestness@gmail.com { } 1196221Snate@binkert.org 1204329Sktlim@umich.edu // Hold onto data pointer 1214329Sktlim@umich.edu uint8_t *data; 1228850Sandreas.hansson@arm.com }; 1232292SN/A 1242292SN/A PacketPtr retryPkt; 1252292SN/A 1262292SN/A bool accessRetry; 1272292SN/A 1282292SN/A // 1292292SN/A // The dmaOustanding flag enforces only one dma at a time 1302292SN/A // 1312292SN/A bool dmaOutstanding; 1322292SN/A 1332292SN/A unsigned size; // size of testing memory region 1342292SN/A 1352292SN/A unsigned percentReads; // target percentage of read accesses 1362727Sktlim@umich.edu unsigned percentFunctional; // target percentage of functional accesses 1372727Sktlim@umich.edu unsigned percentUncacheable; 1382727Sktlim@umich.edu 1396221Snate@binkert.org bool issueDmas; 1402727Sktlim@umich.edu 1412727Sktlim@umich.edu /** Request id for all generated traffic */ 1422727Sktlim@umich.edu MasterID masterId; 1432727Sktlim@umich.edu 1442727Sktlim@umich.edu int id; 1452727Sktlim@umich.edu 1466221Snate@binkert.org std::set<unsigned> outstandingAddrs; 1472292SN/A 1482292SN/A unsigned blockSize; 1492292SN/A 1502292SN/A Addr blockAddrMask; 1512292SN/A 1522292SN/A Addr blockAddr(Addr addr) 1532307SN/A { 1549444SAndreas.Sandberg@ARM.com return (addr & ~blockAddrMask); 1552307SN/A } 1569444SAndreas.Sandberg@ARM.com 1579444SAndreas.Sandberg@ARM.com Addr traceBlockAddr; 1589444SAndreas.Sandberg@ARM.com 1599444SAndreas.Sandberg@ARM.com Addr baseAddr1; // fix this to option 1609444SAndreas.Sandberg@ARM.com Addr baseAddr2; // fix this to option 1619444SAndreas.Sandberg@ARM.com Addr uncacheAddr; 1629444SAndreas.Sandberg@ARM.com 1639444SAndreas.Sandberg@ARM.com unsigned progressInterval; // frequency of progress reports 1649444SAndreas.Sandberg@ARM.com Tick nextProgressMessage; // access # for next progress report 1659444SAndreas.Sandberg@ARM.com 1669444SAndreas.Sandberg@ARM.com unsigned percentSourceUnaligned; 1679444SAndreas.Sandberg@ARM.com unsigned percentDestUnaligned; 1689444SAndreas.Sandberg@ARM.com 1699444SAndreas.Sandberg@ARM.com Tick noResponseCycles; 1709444SAndreas.Sandberg@ARM.com 1712307SN/A uint64_t numReads; 1729444SAndreas.Sandberg@ARM.com uint64_t numWrites; 1739444SAndreas.Sandberg@ARM.com uint64_t maxLoads; 1749444SAndreas.Sandberg@ARM.com 1759444SAndreas.Sandberg@ARM.com bool atomic; 1769444SAndreas.Sandberg@ARM.com bool suppress_func_warnings; 1779444SAndreas.Sandberg@ARM.com 1789444SAndreas.Sandberg@ARM.com Stats::Scalar numReadsStat; 1799444SAndreas.Sandberg@ARM.com Stats::Scalar numWritesStat; 1809444SAndreas.Sandberg@ARM.com Stats::Scalar numCopiesStat; 1819444SAndreas.Sandberg@ARM.com 1829444SAndreas.Sandberg@ARM.com // called by MemCompleteEvent::process() 1839444SAndreas.Sandberg@ARM.com void completeRequest(PacketPtr pkt); 1842307SN/A 1852307SN/A void sendPkt(PacketPtr pkt); 1862307SN/A 1872307SN/A void doRetry(); 1882307SN/A 1892307SN/A friend class MemCompleteEvent; 1906221Snate@binkert.org}; 1912307SN/A 1922307SN/A#endif // __CPU_MEMTEST_MEMTEST_HH__ 1932307SN/A