memtest.hh revision 8922:17f037ad8918 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Steve Reinhardt
30 */
31
32#ifndef __CPU_MEMTEST_MEMTEST_HH__
33#define __CPU_MEMTEST_MEMTEST_HH__
34
35#include <set>
36
37#include "base/fast_alloc.hh"
38#include "base/statistics.hh"
39#include "mem/mem_object.hh"
40#include "mem/port.hh"
41#include "mem/port_proxy.hh"
42#include "params/MemTest.hh"
43#include "sim/eventq.hh"
44#include "sim/sim_exit.hh"
45#include "sim/sim_object.hh"
46#include "sim/stats.hh"
47
48class Packet;
49class MemTest : public MemObject
50{
51  public:
52    typedef MemTestParams Params;
53    MemTest(const Params *p);
54
55    virtual void init();
56
57    // register statistics
58    virtual void regStats();
59
60    inline Tick ticks(int numCycles) const { return numCycles; }
61
62    // main simulation loop (one cycle)
63    void tick();
64
65    virtual MasterPort &getMasterPort(const std::string &if_name,
66                                      int idx = -1);
67
68    /**
69     * Print state of address in memory system via PrintReq (for
70     * debugging).
71     */
72    void printAddr(Addr a);
73
74  protected:
75    class TickEvent : public Event
76    {
77      private:
78        MemTest *cpu;
79
80      public:
81        TickEvent(MemTest *c) : Event(CPU_Tick_Pri), cpu(c) {}
82        void process() { cpu->tick(); }
83        virtual const char *description() const { return "MemTest tick"; }
84    };
85
86    TickEvent tickEvent;
87
88    class CpuPort : public MasterPort
89    {
90        MemTest *memtest;
91
92      public:
93
94        CpuPort(const std::string &_name, MemTest *_memtest)
95            : MasterPort(_name, _memtest), memtest(_memtest)
96        { }
97
98      protected:
99
100        virtual bool recvTiming(PacketPtr pkt);
101
102        virtual Tick recvAtomic(PacketPtr pkt);
103
104        virtual void recvFunctional(PacketPtr pkt);
105
106        virtual void recvRetry();
107    };
108
109    CpuPort cachePort;
110    CpuPort funcPort;
111    PortProxy funcProxy;
112
113    class MemTestSenderState : public Packet::SenderState, public FastAlloc
114    {
115      public:
116        /** Constructor. */
117        MemTestSenderState(uint8_t *_data)
118            : data(_data)
119        { }
120
121        // Hold onto data pointer
122        uint8_t *data;
123    };
124
125    PacketPtr retryPkt;
126
127    bool accessRetry;
128
129    //
130    // The dmaOustanding flag enforces only one dma at a time
131    //
132    bool dmaOutstanding;
133
134    unsigned size;              // size of testing memory region
135
136    unsigned percentReads;      // target percentage of read accesses
137    unsigned percentFunctional; // target percentage of functional accesses
138    unsigned percentUncacheable;
139
140    bool issueDmas;
141
142    /** Request id for all generated traffic */
143    MasterID masterId;
144
145    int id;
146
147    std::set<unsigned> outstandingAddrs;
148
149    unsigned blockSize;
150
151    Addr blockAddrMask;
152
153    Addr blockAddr(Addr addr)
154    {
155        return (addr & ~blockAddrMask);
156    }
157
158    Addr traceBlockAddr;
159
160    Addr baseAddr1;             // fix this to option
161    Addr baseAddr2;             // fix this to option
162    Addr uncacheAddr;
163
164    unsigned progressInterval;  // frequency of progress reports
165    Tick nextProgressMessage;   // access # for next progress report
166
167    unsigned percentSourceUnaligned;
168    unsigned percentDestUnaligned;
169
170    Tick noResponseCycles;
171
172    uint64_t numReads;
173    uint64_t numWrites;
174    uint64_t maxLoads;
175
176    bool atomic;
177    bool suppress_func_warnings;
178
179    Stats::Scalar numReadsStat;
180    Stats::Scalar numWritesStat;
181    Stats::Scalar numCopiesStat;
182
183    // called by MemCompleteEvent::process()
184    void completeRequest(PacketPtr pkt);
185
186    void sendPkt(PacketPtr pkt);
187
188    void doRetry();
189
190    friend class MemCompleteEvent;
191};
192
193#endif // __CPU_MEMTEST_MEMTEST_HH__
194
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