memtest.hh revision 8436
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 * Steve Reinhardt 30 */ 31 32#ifndef __CPU_MEMTEST_MEMTEST_HH__ 33#define __CPU_MEMTEST_MEMTEST_HH__ 34 35#include <set> 36 37#include "base/fast_alloc.hh" 38#include "base/statistics.hh" 39#include "mem/mem_object.hh" 40#include "mem/port.hh" 41#include "params/MemTest.hh" 42#include "sim/eventq.hh" 43#include "sim/sim_exit.hh" 44#include "sim/sim_object.hh" 45#include "sim/stats.hh" 46 47class Packet; 48class MemTest : public MemObject 49{ 50 public: 51 typedef MemTestParams Params; 52 MemTest(const Params *p); 53 54 virtual void init(); 55 56 // register statistics 57 virtual void regStats(); 58 59 inline Tick ticks(int numCycles) const { return numCycles; } 60 61 // main simulation loop (one cycle) 62 void tick(); 63 64 virtual Port *getPort(const std::string &if_name, int idx = -1); 65 66 /** 67 * Print state of address in memory system via PrintReq (for 68 * debugging). 69 */ 70 void printAddr(Addr a); 71 72 protected: 73 class TickEvent : public Event 74 { 75 private: 76 MemTest *cpu; 77 78 public: 79 TickEvent(MemTest *c) : Event(CPU_Tick_Pri), cpu(c) {} 80 void process() { cpu->tick(); } 81 virtual const char *description() const { return "MemTest tick"; } 82 }; 83 84 TickEvent tickEvent; 85 86 class CpuPort : public Port 87 { 88 MemTest *memtest; 89 90 public: 91 92 CpuPort(const std::string &_name, MemTest *_memtest) 93 : Port(_name, _memtest), memtest(_memtest) 94 { } 95 96 bool snoopRangeSent; 97 98 protected: 99 100 virtual bool recvTiming(PacketPtr pkt); 101 102 virtual Tick recvAtomic(PacketPtr pkt); 103 104 virtual void recvFunctional(PacketPtr pkt); 105 106 virtual void recvStatusChange(Status status); 107 108 virtual void recvRetry(); 109 110 virtual void getDeviceAddressRanges(AddrRangeList &resp, 111 bool &snoop) 112 { resp.clear(); snoop = false; } 113 }; 114 115 CpuPort cachePort; 116 CpuPort funcPort; 117 118 bool snoopRangeSent; 119 120 class MemTestSenderState : public Packet::SenderState, public FastAlloc 121 { 122 public: 123 /** Constructor. */ 124 MemTestSenderState(uint8_t *_data) 125 : data(_data) 126 { } 127 128 // Hold onto data pointer 129 uint8_t *data; 130 }; 131 132 PacketPtr retryPkt; 133 134 bool accessRetry; 135 136 // 137 // The dmaOustanding flag enforces only one dma at a time 138 // 139 bool dmaOutstanding; 140 141 unsigned size; // size of testing memory region 142 143 unsigned percentReads; // target percentage of read accesses 144 unsigned percentFunctional; // target percentage of functional accesses 145 unsigned percentUncacheable; 146 147 bool issueDmas; 148 149 int id; 150 151 std::set<unsigned> outstandingAddrs; 152 153 unsigned blockSize; 154 155 Addr blockAddrMask; 156 157 Addr blockAddr(Addr addr) 158 { 159 return (addr & ~blockAddrMask); 160 } 161 162 Addr traceBlockAddr; 163 164 Addr baseAddr1; // fix this to option 165 Addr baseAddr2; // fix this to option 166 Addr uncacheAddr; 167 168 unsigned progressInterval; // frequency of progress reports 169 Tick nextProgressMessage; // access # for next progress report 170 171 unsigned percentSourceUnaligned; 172 unsigned percentDestUnaligned; 173 174 Tick noResponseCycles; 175 176 uint64_t numReads; 177 uint64_t numWrites; 178 uint64_t maxLoads; 179 180 bool atomic; 181 bool suppress_func_warnings; 182 183 Stats::Scalar numReadsStat; 184 Stats::Scalar numWritesStat; 185 Stats::Scalar numCopiesStat; 186 187 // called by MemCompleteEvent::process() 188 void completeRequest(PacketPtr pkt); 189 190 void sendPkt(PacketPtr pkt); 191 192 void doRetry(); 193 194 friend class MemCompleteEvent; 195}; 196 197#endif // __CPU_MEMTEST_MEMTEST_HH__ 198 199 200 201