memtest.hh revision 3262
13534Sgblack@eecs.umich.edu/* 23534Sgblack@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 33534Sgblack@eecs.umich.edu * All rights reserved. 43534Sgblack@eecs.umich.edu * 53534Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63534Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73534Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83534Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93534Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103534Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113534Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123534Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133534Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143534Sgblack@eecs.umich.edu * this software without specific prior written permission. 153534Sgblack@eecs.umich.edu * 163534Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173534Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183534Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193534Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203534Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213534Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223534Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233534Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243534Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253534Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263534Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273534Sgblack@eecs.umich.edu * 283534Sgblack@eecs.umich.edu * Authors: Erik Hallnor 293534Sgblack@eecs.umich.edu * Steve Reinhardt 303534Sgblack@eecs.umich.edu */ 313534Sgblack@eecs.umich.edu 324202Sbinkertn@umich.edu#ifndef __CPU_MEMTEST_MEMTEST_HH__ 333534Sgblack@eecs.umich.edu#define __CPU_MEMTEST_MEMTEST_HH__ 344202Sbinkertn@umich.edu 354202Sbinkertn@umich.edu#include <set> 364202Sbinkertn@umich.edu 374202Sbinkertn@umich.edu#include "base/statistics.hh" 384202Sbinkertn@umich.edu//#include "mem/functional/functional.hh" 394202Sbinkertn@umich.edu//#include "mem/mem_interface.hh" 404202Sbinkertn@umich.edu#include "sim/eventq.hh" 414202Sbinkertn@umich.edu#include "sim/sim_exit.hh" 424202Sbinkertn@umich.edu#include "sim/sim_object.hh" 434202Sbinkertn@umich.edu#include "sim/stats.hh" 444202Sbinkertn@umich.edu#include "mem/mem_object.hh" 454202Sbinkertn@umich.edu#include "mem/port.hh" 464202Sbinkertn@umich.edu 474202Sbinkertn@umich.educlass Packet; 484202Sbinkertn@umich.educlass MemTest : public MemObject 494202Sbinkertn@umich.edu{ 504202Sbinkertn@umich.edu public: 514202Sbinkertn@umich.edu 524202Sbinkertn@umich.edu MemTest(const std::string &name, 534202Sbinkertn@umich.edu// MemInterface *_cache_interface, 544202Sbinkertn@umich.edu// PhysicalMemory *main_mem, 554202Sbinkertn@umich.edu// PhysicalMemory *check_mem, 564202Sbinkertn@umich.edu unsigned _memorySize, 574202Sbinkertn@umich.edu unsigned _percentReads, 58// unsigned _percentCopies, 59 unsigned _percentUncacheable, 60 unsigned _progressInterval, 61 unsigned _percentSourceUnaligned, 62 unsigned _percentDestUnaligned, 63 Addr _traceAddr, 64 Counter _max_loads, 65 bool _atomic); 66 67 virtual void init(); 68 69 // register statistics 70 virtual void regStats(); 71 72 inline Tick cycles(int numCycles) const { return numCycles; } 73 74 // main simulation loop (one cycle) 75 void tick(); 76 77 virtual Port *getPort(const std::string &if_name, int idx = -1); 78 79 protected: 80 class TickEvent : public Event 81 { 82 private: 83 MemTest *cpu; 84 public: 85 TickEvent(MemTest *c) 86 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {} 87 void process() {cpu->tick();} 88 virtual const char *description() { return "tick event"; } 89 }; 90 91 TickEvent tickEvent; 92 class CpuPort : public Port 93 { 94 95 MemTest *memtest; 96 97 public: 98 99 CpuPort(const std::string &_name, MemTest *_memtest) 100 : Port(_name), memtest(_memtest) 101 { } 102 103 protected: 104 105 virtual bool recvTiming(Packet *pkt); 106 107 virtual Tick recvAtomic(Packet *pkt); 108 109 virtual void recvFunctional(Packet *pkt); 110 111 virtual void recvStatusChange(Status status); 112 113 virtual void recvRetry(); 114 115 virtual void getDeviceAddressRanges(AddrRangeList &resp, 116 AddrRangeList &snoop) 117 { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); } 118 }; 119 120 CpuPort cachePort; 121 CpuPort funcPort; 122 123 class MemTestSenderState : public Packet::SenderState 124 { 125 public: 126 /** Constructor. */ 127 MemTestSenderState(uint8_t *_data) 128 : data(_data) 129 { } 130 131 // Hold onto data pointer 132 uint8_t *data; 133 }; 134 135// Request *dataReq; 136 Packet *retryPkt; 137// MemInterface *cacheInterface; 138// PhysicalMemory *mainMem; 139// PhysicalMemory *checkMem; 140// SimpleThread *thread; 141 142 bool accessRetry; 143 144 unsigned size; // size of testing memory region 145 146 unsigned percentReads; // target percentage of read accesses 147// unsigned percentCopies; // target percentage of copy accesses 148 unsigned percentUncacheable; 149 150 int id; 151 152 std::set<unsigned> outstandingAddrs; 153 154 unsigned blockSize; 155 156 Addr blockAddrMask; 157 158 Addr blockAddr(Addr addr) 159 { 160 return (addr & ~blockAddrMask); 161 } 162 163 Addr traceBlockAddr; 164 165 Addr baseAddr1; // fix this to option 166 Addr baseAddr2; // fix this to option 167 Addr uncacheAddr; 168 169 unsigned progressInterval; // frequency of progress reports 170 Tick nextProgressMessage; // access # for next progress report 171 172 unsigned percentSourceUnaligned; 173 unsigned percentDestUnaligned; 174 175 Tick noResponseCycles; 176 177 uint64_t numReads; 178 uint64_t maxLoads; 179 180 bool atomic; 181 182 Stats::Scalar<> numReadsStat; 183 Stats::Scalar<> numWritesStat; 184 Stats::Scalar<> numCopiesStat; 185 186 // called by MemCompleteEvent::process() 187 void completeRequest(Packet *pkt); 188 189 void sendPkt(Packet *pkt); 190 191 void doRetry(); 192 193 friend class MemCompleteEvent; 194}; 195 196#endif // __CPU_MEMTEST_MEMTEST_HH__ 197 198 199 200