memtest.hh revision 13892 
1/*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 *          Steve Reinhardt
42 *          Andreas Hansson
43 */
44
45#ifndef __CPU_MEMTEST_MEMTEST_HH__
46#define __CPU_MEMTEST_MEMTEST_HH__
47
48#include <set>
49#include <unordered_map>
50
51#include "base/statistics.hh"
52#include "mem/port.hh"
53#include "params/MemTest.hh"
54#include "sim/clocked_object.hh"
55#include "sim/eventq.hh"
56#include "sim/stats.hh"
57
58/**
59 * The MemTest class tests a cache coherent memory system by
60 * generating false sharing and verifying the read data against a
61 * reference updated on the completion of writes. Each tester reads
62 * and writes a specific byte in a cache line, as determined by its
63 * unique id. Thus, all requests issued by the MemTest instance are a
64 * single byte and a specific address is only ever touched by a single
65 * tester.
66 *
67 * In addition to verifying the data, the tester also has timeouts for
68 * both requests and responses, thus checking that the memory-system
69 * is making progress.
70 */
71class MemTest : public ClockedObject
72{
73
74  public:
75
76    typedef MemTestParams Params;
77    MemTest(const Params *p);
78
79    void regStats() override;
80
81    Port &getPort(const std::string &if_name,
82                  PortID idx=InvalidPortID) override;
83
84  protected:
85
86    void tick();
87
88    EventFunctionWrapper tickEvent;
89
90    void noRequest();
91
92    EventFunctionWrapper noRequestEvent;
93
94    void noResponse();
95
96    EventFunctionWrapper noResponseEvent;
97
98    class CpuPort : public MasterPort
99    {
100        MemTest &memtest;
101
102      public:
103
104        CpuPort(const std::string &_name, MemTest &_memtest)
105            : MasterPort(_name, &_memtest), memtest(_memtest)
106        { }
107
108      protected:
109
110        bool recvTimingResp(PacketPtr pkt);
111
112        void recvTimingSnoopReq(PacketPtr pkt) { }
113
114        void recvFunctionalSnoop(PacketPtr pkt) { }
115
116        Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
117
118        void recvReqRetry();
119    };
120
121    CpuPort port;
122
123    PacketPtr retryPkt;
124
125    const unsigned size;
126
127    const Cycles interval;
128
129    const unsigned percentReads;
130    const unsigned percentFunctional;
131    const unsigned percentUncacheable;
132
133    /** Request id for all generated traffic */
134    MasterID masterId;
135
136    unsigned int id;
137
138    std::set<Addr> outstandingAddrs;
139
140    // store the expected value for the addresses we have touched
141    std::unordered_map<Addr, uint8_t> referenceData;
142
143    const unsigned blockSize;
144
145    const Addr blockAddrMask;
146
147    /**
148     * Get the block aligned address.
149     *
150     * @param addr Address to align
151     * @return The block aligned address
152     */
153    Addr blockAlign(Addr addr) const
154    {
155        return (addr & ~blockAddrMask);
156    }
157
158    Addr baseAddr1;
159    Addr baseAddr2;
160    Addr uncacheAddr;
161
162    const unsigned progressInterval;  // frequency of progress reports
163    const Cycles progressCheck;
164    Tick nextProgressMessage;   // access # for next progress report
165
166    uint64_t numReads;
167    uint64_t numWrites;
168    const uint64_t maxLoads;
169
170    const bool atomic;
171
172    const bool suppressFuncWarnings;
173
174    Stats::Scalar numReadsStat;
175    Stats::Scalar numWritesStat;
176
177    /**
178     * Complete a request by checking the response.
179     *
180     * @param pkt Response packet
181     * @param functional Whether the access was functional or not
182     */
183    void completeRequest(PacketPtr pkt, bool functional = false);
184
185    bool sendPkt(PacketPtr pkt);
186
187    void recvRetry();
188
189};
190
191#endif // __CPU_MEMTEST_MEMTEST_HH__
192