memtest.hh revision 1298
1360SN/A/*
210850SGiacomo.Gabrielli@arm.com * Copyright (c) 2002-2004 The Regents of The University of Michigan
310796Sbrandon.potter@amd.com * All rights reserved.
410027SChris.Adeniyi-Jones@arm.com *
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610027SChris.Adeniyi-Jones@arm.com * modification, are permitted provided that the following conditions are
710027SChris.Adeniyi-Jones@arm.com * met: redistributions of source code must retain the above copyright
810027SChris.Adeniyi-Jones@arm.com * notice, this list of conditions and the following disclaimer;
910027SChris.Adeniyi-Jones@arm.com * redistributions in binary form must reproduce the above copyright
1010027SChris.Adeniyi-Jones@arm.com * notice, this list of conditions and the following disclaimer in the
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1410027SChris.Adeniyi-Jones@arm.com * this software without specific prior written permission.
151458SN/A *
16360SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17360SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18360SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19360SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20360SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26360SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27360SN/A */
28360SN/A
29360SN/A#ifndef __MEMTEST_HH__
30360SN/A#define __MEMTEST_HH__
31360SN/A
32360SN/A#include <set>
33360SN/A
34360SN/A#include "base/statistics.hh"
35360SN/A#include "cpu/base_cpu.hh"
36360SN/A#include "cpu/exec_context.hh"
37360SN/A#include "mem/functional_mem/functional_memory.hh"
38360SN/A#include "mem/mem_interface.hh"
39360SN/A#include "sim/sim_object.hh"
402665Ssaidi@eecs.umich.edu#include "sim/stats.hh"
412665Ssaidi@eecs.umich.edu
422665Ssaidi@eecs.umich.educlass MemTest : public BaseCPU
43360SN/A{
44360SN/A  public:
451354SN/A
461354SN/A    MemTest(const std::string &name,
47360SN/A            MemInterface *_cache_interface,
4812018Sandreas.sandberg@arm.com            FunctionalMemory *main_mem,
4912018Sandreas.sandberg@arm.com            FunctionalMemory *check_mem,
5012018Sandreas.sandberg@arm.com            unsigned _memorySize,
5112018Sandreas.sandberg@arm.com            unsigned _percentReads,
5212018Sandreas.sandberg@arm.com            unsigned _percentCopies,
5312018Sandreas.sandberg@arm.com            unsigned _percentUncacheable,
5412018Sandreas.sandberg@arm.com            unsigned _progressInterval,
552064SN/A            unsigned _percentSourceUnaligned,
5612018Sandreas.sandberg@arm.com            unsigned _percentDestUnaligned,
5712018Sandreas.sandberg@arm.com            Addr _traceAddr,
5812018Sandreas.sandberg@arm.com            Counter max_loads_any_thread,
5912018Sandreas.sandberg@arm.com            Counter max_loads_all_threads);
6012018Sandreas.sandberg@arm.com
6112018Sandreas.sandberg@arm.com    // register statistics
6211799Sbrandon.potter@amd.com    virtual void regStats();
6312018Sandreas.sandberg@arm.com    // main simulation loop (one cycle)
6412018Sandreas.sandberg@arm.com    void tick();
6512018Sandreas.sandberg@arm.com
6612018Sandreas.sandberg@arm.com  protected:
6712018Sandreas.sandberg@arm.com    class TickEvent : public Event
6812018Sandreas.sandberg@arm.com    {
6911799Sbrandon.potter@amd.com      private:
70360SN/A        MemTest *cpu;
71360SN/A      public:
72360SN/A        TickEvent(MemTest *c)
73360SN/A            : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {}
74360SN/A        void process() {cpu->tick();}
75360SN/A        virtual const char *description() { return "tick event"; }
761809SN/A    };
7711800Sbrandon.potter@amd.com
7811392Sbrandon.potter@amd.com    TickEvent tickEvent;
791809SN/A
8011392Sbrandon.potter@amd.com    MemInterface *cacheInterface;
8113902Sbrandon.potter@amd.com    FunctionalMemory *mainMem;
8213570Sbrandon.potter@amd.com    FunctionalMemory *checkMem;
8313902Sbrandon.potter@amd.com    ExecContext *xc;
8411383Sbrandon.potter@amd.com
8513568Sbrandon.potter@amd.com    unsigned size;		// size of testing memory region
863113Sgblack@eecs.umich.edu
8713902Sbrandon.potter@amd.com    unsigned percentReads;	// target percentage of read accesses
8811799Sbrandon.potter@amd.com    unsigned percentCopies;	// target percentage of copy accesses
8911759Sbrandon.potter@amd.com    unsigned percentUncacheable;
9013902Sbrandon.potter@amd.com
9111812Sbaz21@cam.ac.uk    int id;
9211812Sbaz21@cam.ac.uk
9313902Sbrandon.potter@amd.com    std::set<unsigned> outstandingAddrs;
9411799Sbrandon.potter@amd.com
958229Snate@binkert.org    unsigned blockSize;
9613570Sbrandon.potter@amd.com
978229Snate@binkert.org    Addr blockAddrMask;
9811594Santhony.gutierrez@amd.com
997075Snate@binkert.org    Addr blockAddr(Addr addr)
1008229Snate@binkert.org    {
10111856Sbrandon.potter@amd.com        return (addr & ~blockAddrMask);
1027075Snate@binkert.org    }
103360SN/A
10412461Sgabeblack@google.com    Addr traceBlockAddr;
10511886Sbrandon.potter@amd.com
10611800Sbrandon.potter@amd.com    Addr baseAddr1;		// fix this to option
10711392Sbrandon.potter@amd.com    Addr baseAddr2;		// fix this to option
10812334Sgabeblack@google.com    Addr uncacheAddr;
1091354SN/A
1106216Snate@binkert.org    unsigned progressInterval;	// frequency of progress reports
1116658Snate@binkert.org    Tick nextProgressMessage;	// access # for next progress report
1122474SN/A
1132680Sktlim@umich.edu    unsigned percentSourceUnaligned;
1148229Snate@binkert.org    unsigned percentDestUnaligned;
11511886Sbrandon.potter@amd.com
11610496Ssteve.reinhardt@amd.com    Tick noResponseCycles;
11711911SBrandon.Potter@amd.com
1188229Snate@binkert.org    uint64_t numReads;
11911794Sbrandon.potter@amd.com    Stats::Scalar<> numReadsStat;
12011886Sbrandon.potter@amd.com    Stats::Scalar<> numWritesStat;
12110497Ssteve.reinhardt@amd.com    Stats::Scalar<> numCopiesStat;
12211794Sbrandon.potter@amd.com
123360SN/A    // called by MemCompleteEvent::process()
12413629SAndrea.Mondelli@ucf.edu    void completeRequest(MemReqPtr &req, uint8_t *data);
12513629SAndrea.Mondelli@ucf.edu
12613629SAndrea.Mondelli@ucf.edu    friend class MemCompleteEvent;
12713629SAndrea.Mondelli@ucf.edu};
128360SN/A
129360SN/A
130360SN/Aclass MemCompleteEvent : public Event
131360SN/A{
132360SN/A    MemReqPtr req;
133360SN/A    uint8_t *data;
134360SN/A    MemTest *tester;
135360SN/A
136360SN/A  public:
137378SN/A
1381706SN/A    MemCompleteEvent(MemReqPtr &_req, uint8_t *_data, MemTest *_tester)
13911851Sbrandon.potter@amd.com        : Event(&mainEventQueue),
140378SN/A          req(_req), data(_data), tester(_tester)
141378SN/A    {
142378SN/A    }
143378SN/A
144378SN/A    void process();
1451706SN/A
14611851Sbrandon.potter@amd.com    virtual const char *description();
147360SN/A};
14811760Sbrandon.potter@amd.com
14911760Sbrandon.potter@amd.com#endif // __MEMTEST_HH__
15011851Sbrandon.potter@amd.com
15111760Sbrandon.potter@amd.com
1526109Ssanchezd@stanford.edu
1531706SN/A