memtest.hh revision 12085 
1/*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 *          Steve Reinhardt
42 *          Andreas Hansson
43 */
44
45#ifndef __CPU_MEMTEST_MEMTEST_HH__
46#define __CPU_MEMTEST_MEMTEST_HH__
47
48#include <set>
49#include <unordered_map>
50
51#include "base/statistics.hh"
52#include "mem/mem_object.hh"
53#include "params/MemTest.hh"
54#include "sim/eventq.hh"
55#include "sim/stats.hh"
56
57/**
58 * The MemTest class tests a cache coherent memory system by
59 * generating false sharing and verifying the read data against a
60 * reference updated on the completion of writes. Each tester reads
61 * and writes a specific byte in a cache line, as determined by its
62 * unique id. Thus, all requests issued by the MemTest instance are a
63 * single byte and a specific address is only ever touched by a single
64 * tester.
65 *
66 * In addition to verifying the data, the tester also has timeouts for
67 * both requests and responses, thus checking that the memory-system
68 * is making progress.
69 */
70class MemTest : public MemObject
71{
72
73  public:
74
75    typedef MemTestParams Params;
76    MemTest(const Params *p);
77
78    virtual void regStats();
79
80    virtual BaseMasterPort &getMasterPort(const std::string &if_name,
81                                          PortID idx = InvalidPortID);
82
83  protected:
84
85    void tick();
86
87    EventFunctionWrapper tickEvent;
88
89    void noRequest();
90
91    EventFunctionWrapper noRequestEvent;
92
93    void noResponse();
94
95    EventFunctionWrapper noResponseEvent;
96
97    class CpuPort : public MasterPort
98    {
99        MemTest &memtest;
100
101      public:
102
103        CpuPort(const std::string &_name, MemTest &_memtest)
104            : MasterPort(_name, &_memtest), memtest(_memtest)
105        { }
106
107      protected:
108
109        bool recvTimingResp(PacketPtr pkt);
110
111        void recvTimingSnoopReq(PacketPtr pkt) { }
112
113        void recvFunctionalSnoop(PacketPtr pkt) { }
114
115        Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
116
117        void recvReqRetry();
118    };
119
120    CpuPort port;
121
122    PacketPtr retryPkt;
123
124    const unsigned size;
125
126    const Cycles interval;
127
128    const unsigned percentReads;
129    const unsigned percentFunctional;
130    const unsigned percentUncacheable;
131
132    /** Request id for all generated traffic */
133    MasterID masterId;
134
135    unsigned int id;
136
137    std::set<Addr> outstandingAddrs;
138
139    // store the expected value for the addresses we have touched
140    std::unordered_map<Addr, uint8_t> referenceData;
141
142    const unsigned blockSize;
143
144    const Addr blockAddrMask;
145
146    /**
147     * Get the block aligned address.
148     *
149     * @param addr Address to align
150     * @return The block aligned address
151     */
152    Addr blockAlign(Addr addr) const
153    {
154        return (addr & ~blockAddrMask);
155    }
156
157    Addr baseAddr1;
158    Addr baseAddr2;
159    Addr uncacheAddr;
160
161    const unsigned progressInterval;  // frequency of progress reports
162    const Cycles progressCheck;
163    Tick nextProgressMessage;   // access # for next progress report
164
165    uint64_t numReads;
166    uint64_t numWrites;
167    const uint64_t maxLoads;
168
169    const bool atomic;
170
171    const bool suppressFuncWarnings;
172
173    Stats::Scalar numReadsStat;
174    Stats::Scalar numWritesStat;
175
176    /**
177     * Complete a request by checking the response.
178     *
179     * @param pkt Response packet
180     * @param functional Whether the access was functional or not
181     */
182    void completeRequest(PacketPtr pkt, bool functional = false);
183
184    bool sendPkt(PacketPtr pkt);
185
186    void recvRetry();
187
188};
189
190#endif // __CPU_MEMTEST_MEMTEST_HH__
191