memtest.hh revision 8922
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Erik Hallnor 292665SN/A * Steve Reinhardt 302SN/A */ 312SN/A 321400SN/A#ifndef __CPU_MEMTEST_MEMTEST_HH__ 331400SN/A#define __CPU_MEMTEST_MEMTEST_HH__ 342SN/A 351298SN/A#include <set> 361298SN/A 378229Snate@binkert.org#include "base/fast_alloc.hh" 381298SN/A#include "base/statistics.hh" 398229Snate@binkert.org#include "mem/mem_object.hh" 408229Snate@binkert.org#include "mem/port.hh" 418853Sandreas.hansson@arm.com#include "mem/port_proxy.hh" 425034SN/A#include "params/MemTest.hh" 431400SN/A#include "sim/eventq.hh" 441400SN/A#include "sim/sim_exit.hh" 451298SN/A#include "sim/sim_object.hh" 46695SN/A#include "sim/stats.hh" 472SN/A 483187SN/Aclass Packet; 493187SN/Aclass MemTest : public MemObject 502SN/A{ 512SN/A public: 525034SN/A typedef MemTestParams Params; 535034SN/A MemTest(const Params *p); 542SN/A 553187SN/A virtual void init(); 563187SN/A 572SN/A // register statistics 582SN/A virtual void regStats(); 591634SN/A 605100SN/A inline Tick ticks(int numCycles) const { return numCycles; } 611634SN/A 622SN/A // main simulation loop (one cycle) 632SN/A void tick(); 642SN/A 658922Swilliam.wang@arm.com virtual MasterPort &getMasterPort(const std::string &if_name, 668922Swilliam.wang@arm.com int idx = -1); 673187SN/A 685315SN/A /** 695315SN/A * Print state of address in memory system via PrintReq (for 705315SN/A * debugging). 715315SN/A */ 725314SN/A void printAddr(Addr a); 735314SN/A 742SN/A protected: 752SN/A class TickEvent : public Event 762SN/A { 772SN/A private: 782SN/A MemTest *cpu; 795606SN/A 802SN/A public: 815606SN/A TickEvent(MemTest *c) : Event(CPU_Tick_Pri), cpu(c) {} 825606SN/A void process() { cpu->tick(); } 835336SN/A virtual const char *description() const { return "MemTest tick"; } 842SN/A }; 852SN/A 862SN/A TickEvent tickEvent; 874474SN/A 888922Swilliam.wang@arm.com class CpuPort : public MasterPort 893187SN/A { 903187SN/A MemTest *memtest; 913187SN/A 923187SN/A public: 933187SN/A 943187SN/A CpuPort(const std::string &_name, MemTest *_memtest) 958922Swilliam.wang@arm.com : MasterPort(_name, _memtest), memtest(_memtest) 963187SN/A { } 973187SN/A 983187SN/A protected: 993187SN/A 1003349SN/A virtual bool recvTiming(PacketPtr pkt); 1013187SN/A 1023349SN/A virtual Tick recvAtomic(PacketPtr pkt); 1033187SN/A 1043349SN/A virtual void recvFunctional(PacketPtr pkt); 1053187SN/A 1063187SN/A virtual void recvRetry(); 1073187SN/A }; 1083187SN/A 1093187SN/A CpuPort cachePort; 1103187SN/A CpuPort funcPort; 1118853Sandreas.hansson@arm.com PortProxy funcProxy; 1123187SN/A 1135386SN/A class MemTestSenderState : public Packet::SenderState, public FastAlloc 1143187SN/A { 1153187SN/A public: 1163187SN/A /** Constructor. */ 1173187SN/A MemTestSenderState(uint8_t *_data) 1183187SN/A : data(_data) 1193187SN/A { } 1203187SN/A 1213187SN/A // Hold onto data pointer 1223187SN/A uint8_t *data; 1233187SN/A }; 1243187SN/A 1253349SN/A PacketPtr retryPkt; 1263187SN/A 1273187SN/A bool accessRetry; 1287544SN/A 1297544SN/A // 1307544SN/A // The dmaOustanding flag enforces only one dma at a time 1317544SN/A // 1327544SN/A bool dmaOutstanding; 1332SN/A 1345543SN/A unsigned size; // size of testing memory region 1352SN/A 1365543SN/A unsigned percentReads; // target percentage of read accesses 1375543SN/A unsigned percentFunctional; // target percentage of functional accesses 1382SN/A unsigned percentUncacheable; 1392SN/A 1407544SN/A bool issueDmas; 1417544SN/A 1428832SAli.Saidi@ARM.com /** Request id for all generated traffic */ 1438832SAli.Saidi@ARM.com MasterID masterId; 1448832SAli.Saidi@ARM.com 1451298SN/A int id; 1461298SN/A 1471298SN/A std::set<unsigned> outstandingAddrs; 1481298SN/A 1492SN/A unsigned blockSize; 1502SN/A 1512SN/A Addr blockAddrMask; 1522SN/A 1532SN/A Addr blockAddr(Addr addr) 1542SN/A { 1552SN/A return (addr & ~blockAddrMask); 1562SN/A } 1572SN/A 1582SN/A Addr traceBlockAddr; 1592SN/A 1605543SN/A Addr baseAddr1; // fix this to option 1615543SN/A Addr baseAddr2; // fix this to option 1622SN/A Addr uncacheAddr; 1632SN/A 1645543SN/A unsigned progressInterval; // frequency of progress reports 1655543SN/A Tick nextProgressMessage; // access # for next progress report 1662SN/A 167548SN/A unsigned percentSourceUnaligned; 168548SN/A unsigned percentDestUnaligned; 169548SN/A 1702SN/A Tick noResponseCycles; 1712SN/A 172695SN/A uint64_t numReads; 1738436SBrad.Beckmann@amd.com uint64_t numWrites; 1741400SN/A uint64_t maxLoads; 1753262SN/A 1763262SN/A bool atomic; 1778436SBrad.Beckmann@amd.com bool suppress_func_warnings; 1783262SN/A 1795999SN/A Stats::Scalar numReadsStat; 1805999SN/A Stats::Scalar numWritesStat; 1815999SN/A Stats::Scalar numCopiesStat; 1822SN/A 1832SN/A // called by MemCompleteEvent::process() 1843349SN/A void completeRequest(PacketPtr pkt); 1853187SN/A 1863349SN/A void sendPkt(PacketPtr pkt); 1873262SN/A 1883187SN/A void doRetry(); 1892SN/A 1902SN/A friend class MemCompleteEvent; 1912SN/A}; 1922SN/A 1931400SN/A#endif // __CPU_MEMTEST_MEMTEST_HH__ 1942SN/A 1952SN/A 1962SN/A 197