memtest.hh revision 8853
12SN/A/*
21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Erik Hallnor
292665SN/A *          Steve Reinhardt
302SN/A */
312SN/A
321400SN/A#ifndef __CPU_MEMTEST_MEMTEST_HH__
331400SN/A#define __CPU_MEMTEST_MEMTEST_HH__
342SN/A
351298SN/A#include <set>
361298SN/A
378229Snate@binkert.org#include "base/fast_alloc.hh"
381298SN/A#include "base/statistics.hh"
398229Snate@binkert.org#include "mem/mem_object.hh"
408229Snate@binkert.org#include "mem/port.hh"
418853Sandreas.hansson@arm.com#include "mem/port_proxy.hh"
425034SN/A#include "params/MemTest.hh"
431400SN/A#include "sim/eventq.hh"
441400SN/A#include "sim/sim_exit.hh"
451298SN/A#include "sim/sim_object.hh"
46695SN/A#include "sim/stats.hh"
472SN/A
483187SN/Aclass Packet;
493187SN/Aclass MemTest : public MemObject
502SN/A{
512SN/A  public:
525034SN/A    typedef MemTestParams Params;
535034SN/A    MemTest(const Params *p);
542SN/A
553187SN/A    virtual void init();
563187SN/A
572SN/A    // register statistics
582SN/A    virtual void regStats();
591634SN/A
605100SN/A    inline Tick ticks(int numCycles) const { return numCycles; }
611634SN/A
622SN/A    // main simulation loop (one cycle)
632SN/A    void tick();
642SN/A
653187SN/A    virtual Port *getPort(const std::string &if_name, int idx = -1);
663187SN/A
675315SN/A    /**
685315SN/A     * Print state of address in memory system via PrintReq (for
695315SN/A     * debugging).
705315SN/A     */
715314SN/A    void printAddr(Addr a);
725314SN/A
732SN/A  protected:
742SN/A    class TickEvent : public Event
752SN/A    {
762SN/A      private:
772SN/A        MemTest *cpu;
785606SN/A
792SN/A      public:
805606SN/A        TickEvent(MemTest *c) : Event(CPU_Tick_Pri), cpu(c) {}
815606SN/A        void process() { cpu->tick(); }
825336SN/A        virtual const char *description() const { return "MemTest tick"; }
832SN/A    };
842SN/A
852SN/A    TickEvent tickEvent;
864474SN/A
873187SN/A    class CpuPort : public Port
883187SN/A    {
893187SN/A        MemTest *memtest;
903187SN/A
913187SN/A      public:
923187SN/A
933187SN/A        CpuPort(const std::string &_name, MemTest *_memtest)
943402SN/A            : Port(_name, _memtest), memtest(_memtest)
953187SN/A        { }
963187SN/A
973187SN/A      protected:
983187SN/A
993349SN/A        virtual bool recvTiming(PacketPtr pkt);
1003187SN/A
1013349SN/A        virtual Tick recvAtomic(PacketPtr pkt);
1023187SN/A
1033349SN/A        virtual void recvFunctional(PacketPtr pkt);
1043187SN/A
1058711Sandreas.hansson@arm.com        virtual void recvRangeChange();
1063187SN/A
1073187SN/A        virtual void recvRetry();
1083187SN/A    };
1093187SN/A
1103187SN/A    CpuPort cachePort;
1113187SN/A    CpuPort funcPort;
1128853Sandreas.hansson@arm.com    PortProxy funcProxy;
1133187SN/A
1145386SN/A    class MemTestSenderState : public Packet::SenderState, public FastAlloc
1153187SN/A    {
1163187SN/A      public:
1173187SN/A        /** Constructor. */
1183187SN/A        MemTestSenderState(uint8_t *_data)
1193187SN/A            : data(_data)
1203187SN/A        { }
1213187SN/A
1223187SN/A        // Hold onto data pointer
1233187SN/A        uint8_t *data;
1243187SN/A    };
1253187SN/A
1263349SN/A    PacketPtr retryPkt;
1273187SN/A
1283187SN/A    bool accessRetry;
1297544SN/A
1307544SN/A    //
1317544SN/A    // The dmaOustanding flag enforces only one dma at a time
1327544SN/A    //
1337544SN/A    bool dmaOutstanding;
1342SN/A
1355543SN/A    unsigned size;              // size of testing memory region
1362SN/A
1375543SN/A    unsigned percentReads;      // target percentage of read accesses
1385543SN/A    unsigned percentFunctional; // target percentage of functional accesses
1392SN/A    unsigned percentUncacheable;
1402SN/A
1417544SN/A    bool issueDmas;
1427544SN/A
1438832SAli.Saidi@ARM.com    /** Request id for all generated traffic */
1448832SAli.Saidi@ARM.com    MasterID masterId;
1458832SAli.Saidi@ARM.com
1461298SN/A    int id;
1471298SN/A
1481298SN/A    std::set<unsigned> outstandingAddrs;
1491298SN/A
1502SN/A    unsigned blockSize;
1512SN/A
1522SN/A    Addr blockAddrMask;
1532SN/A
1542SN/A    Addr blockAddr(Addr addr)
1552SN/A    {
1562SN/A        return (addr & ~blockAddrMask);
1572SN/A    }
1582SN/A
1592SN/A    Addr traceBlockAddr;
1602SN/A
1615543SN/A    Addr baseAddr1;             // fix this to option
1625543SN/A    Addr baseAddr2;             // fix this to option
1632SN/A    Addr uncacheAddr;
1642SN/A
1655543SN/A    unsigned progressInterval;  // frequency of progress reports
1665543SN/A    Tick nextProgressMessage;   // access # for next progress report
1672SN/A
168548SN/A    unsigned percentSourceUnaligned;
169548SN/A    unsigned percentDestUnaligned;
170548SN/A
1712SN/A    Tick noResponseCycles;
1722SN/A
173695SN/A    uint64_t numReads;
1748436SBrad.Beckmann@amd.com    uint64_t numWrites;
1751400SN/A    uint64_t maxLoads;
1763262SN/A
1773262SN/A    bool atomic;
1788436SBrad.Beckmann@amd.com    bool suppress_func_warnings;
1793262SN/A
1805999SN/A    Stats::Scalar numReadsStat;
1815999SN/A    Stats::Scalar numWritesStat;
1825999SN/A    Stats::Scalar numCopiesStat;
1832SN/A
1842SN/A    // called by MemCompleteEvent::process()
1853349SN/A    void completeRequest(PacketPtr pkt);
1863187SN/A
1873349SN/A    void sendPkt(PacketPtr pkt);
1883262SN/A
1893187SN/A    void doRetry();
1902SN/A
1912SN/A    friend class MemCompleteEvent;
1922SN/A};
1932SN/A
1941400SN/A#endif // __CPU_MEMTEST_MEMTEST_HH__
1952SN/A
1962SN/A
1972SN/A
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