memtest.hh revision 8711
12SN/A/*
21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Erik Hallnor
292665SN/A *          Steve Reinhardt
302SN/A */
312SN/A
321400SN/A#ifndef __CPU_MEMTEST_MEMTEST_HH__
331400SN/A#define __CPU_MEMTEST_MEMTEST_HH__
342SN/A
351298SN/A#include <set>
361298SN/A
378229Snate@binkert.org#include "base/fast_alloc.hh"
381298SN/A#include "base/statistics.hh"
398229Snate@binkert.org#include "mem/mem_object.hh"
408229Snate@binkert.org#include "mem/port.hh"
415034SN/A#include "params/MemTest.hh"
421400SN/A#include "sim/eventq.hh"
431400SN/A#include "sim/sim_exit.hh"
441298SN/A#include "sim/sim_object.hh"
45695SN/A#include "sim/stats.hh"
462SN/A
473187SN/Aclass Packet;
483187SN/Aclass MemTest : public MemObject
492SN/A{
502SN/A  public:
515034SN/A    typedef MemTestParams Params;
525034SN/A    MemTest(const Params *p);
532SN/A
543187SN/A    virtual void init();
553187SN/A
562SN/A    // register statistics
572SN/A    virtual void regStats();
581634SN/A
595100SN/A    inline Tick ticks(int numCycles) const { return numCycles; }
601634SN/A
612SN/A    // main simulation loop (one cycle)
622SN/A    void tick();
632SN/A
643187SN/A    virtual Port *getPort(const std::string &if_name, int idx = -1);
653187SN/A
665315SN/A    /**
675315SN/A     * Print state of address in memory system via PrintReq (for
685315SN/A     * debugging).
695315SN/A     */
705314SN/A    void printAddr(Addr a);
715314SN/A
722SN/A  protected:
732SN/A    class TickEvent : public Event
742SN/A    {
752SN/A      private:
762SN/A        MemTest *cpu;
775606SN/A
782SN/A      public:
795606SN/A        TickEvent(MemTest *c) : Event(CPU_Tick_Pri), cpu(c) {}
805606SN/A        void process() { cpu->tick(); }
815336SN/A        virtual const char *description() const { return "MemTest tick"; }
822SN/A    };
832SN/A
842SN/A    TickEvent tickEvent;
854474SN/A
863187SN/A    class CpuPort : public Port
873187SN/A    {
883187SN/A        MemTest *memtest;
893187SN/A
903187SN/A      public:
913187SN/A
923187SN/A        CpuPort(const std::string &_name, MemTest *_memtest)
933402SN/A            : Port(_name, _memtest), memtest(_memtest)
943187SN/A        { }
953187SN/A
963187SN/A      protected:
973187SN/A
983349SN/A        virtual bool recvTiming(PacketPtr pkt);
993187SN/A
1003349SN/A        virtual Tick recvAtomic(PacketPtr pkt);
1013187SN/A
1023349SN/A        virtual void recvFunctional(PacketPtr pkt);
1033187SN/A
1048711Sandreas.hansson@arm.com        virtual void recvRangeChange();
1053187SN/A
1063187SN/A        virtual void recvRetry();
1073187SN/A    };
1083187SN/A
1093187SN/A    CpuPort cachePort;
1103187SN/A    CpuPort funcPort;
1113187SN/A
1125386SN/A    class MemTestSenderState : public Packet::SenderState, public FastAlloc
1133187SN/A    {
1143187SN/A      public:
1153187SN/A        /** Constructor. */
1163187SN/A        MemTestSenderState(uint8_t *_data)
1173187SN/A            : data(_data)
1183187SN/A        { }
1193187SN/A
1203187SN/A        // Hold onto data pointer
1213187SN/A        uint8_t *data;
1223187SN/A    };
1233187SN/A
1243349SN/A    PacketPtr retryPkt;
1253187SN/A
1263187SN/A    bool accessRetry;
1277544SN/A
1287544SN/A    //
1297544SN/A    // The dmaOustanding flag enforces only one dma at a time
1307544SN/A    //
1317544SN/A    bool dmaOutstanding;
1322SN/A
1335543SN/A    unsigned size;              // size of testing memory region
1342SN/A
1355543SN/A    unsigned percentReads;      // target percentage of read accesses
1365543SN/A    unsigned percentFunctional; // target percentage of functional accesses
1372SN/A    unsigned percentUncacheable;
1382SN/A
1397544SN/A    bool issueDmas;
1407544SN/A
1411298SN/A    int id;
1421298SN/A
1431298SN/A    std::set<unsigned> outstandingAddrs;
1441298SN/A
1452SN/A    unsigned blockSize;
1462SN/A
1472SN/A    Addr blockAddrMask;
1482SN/A
1492SN/A    Addr blockAddr(Addr addr)
1502SN/A    {
1512SN/A        return (addr & ~blockAddrMask);
1522SN/A    }
1532SN/A
1542SN/A    Addr traceBlockAddr;
1552SN/A
1565543SN/A    Addr baseAddr1;             // fix this to option
1575543SN/A    Addr baseAddr2;             // fix this to option
1582SN/A    Addr uncacheAddr;
1592SN/A
1605543SN/A    unsigned progressInterval;  // frequency of progress reports
1615543SN/A    Tick nextProgressMessage;   // access # for next progress report
1622SN/A
163548SN/A    unsigned percentSourceUnaligned;
164548SN/A    unsigned percentDestUnaligned;
165548SN/A
1662SN/A    Tick noResponseCycles;
1672SN/A
168695SN/A    uint64_t numReads;
1698436SBrad.Beckmann@amd.com    uint64_t numWrites;
1701400SN/A    uint64_t maxLoads;
1713262SN/A
1723262SN/A    bool atomic;
1738436SBrad.Beckmann@amd.com    bool suppress_func_warnings;
1743262SN/A
1755999SN/A    Stats::Scalar numReadsStat;
1765999SN/A    Stats::Scalar numWritesStat;
1775999SN/A    Stats::Scalar numCopiesStat;
1782SN/A
1792SN/A    // called by MemCompleteEvent::process()
1803349SN/A    void completeRequest(PacketPtr pkt);
1813187SN/A
1823349SN/A    void sendPkt(PacketPtr pkt);
1833262SN/A
1843187SN/A    void doRetry();
1852SN/A
1862SN/A    friend class MemCompleteEvent;
1872SN/A};
1882SN/A
1891400SN/A#endif // __CPU_MEMTEST_MEMTEST_HH__
1902SN/A
1912SN/A
1922SN/A
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