memtest.hh revision 5315 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Steve Reinhardt
30 */
31
32#ifndef __CPU_MEMTEST_MEMTEST_HH__
33#define __CPU_MEMTEST_MEMTEST_HH__
34
35#include <set>
36
37#include "base/statistics.hh"
38#include "params/MemTest.hh"
39#include "sim/eventq.hh"
40#include "sim/sim_exit.hh"
41#include "sim/sim_object.hh"
42#include "sim/stats.hh"
43#include "mem/mem_object.hh"
44#include "mem/port.hh"
45
46class Packet;
47class MemTest : public MemObject
48{
49  public:
50    typedef MemTestParams Params;
51    MemTest(const Params *p);
52
53    virtual void init();
54
55    // register statistics
56    virtual void regStats();
57
58    inline Tick ticks(int numCycles) const { return numCycles; }
59
60    // main simulation loop (one cycle)
61    void tick();
62
63    virtual Port *getPort(const std::string &if_name, int idx = -1);
64
65    /**
66     * Print state of address in memory system via PrintReq (for
67     * debugging).
68     */
69    void printAddr(Addr a);
70
71  protected:
72    class TickEvent : public Event
73    {
74      private:
75        MemTest *cpu;
76      public:
77        TickEvent(MemTest *c)
78            : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {}
79        void process() {cpu->tick();}
80        virtual const char *description() { return "MemTest tick"; }
81    };
82
83    TickEvent tickEvent;
84
85    class CpuPort : public Port
86    {
87        MemTest *memtest;
88
89      public:
90
91        CpuPort(const std::string &_name, MemTest *_memtest)
92            : Port(_name, _memtest), memtest(_memtest)
93        { }
94
95        bool snoopRangeSent;
96
97      protected:
98
99        virtual bool recvTiming(PacketPtr pkt);
100
101        virtual Tick recvAtomic(PacketPtr pkt);
102
103        virtual void recvFunctional(PacketPtr pkt);
104
105        virtual void recvStatusChange(Status status);
106
107        virtual void recvRetry();
108
109        virtual void getDeviceAddressRanges(AddrRangeList &resp,
110                                            bool &snoop)
111        { resp.clear(); snoop = false; }
112    };
113
114    CpuPort cachePort;
115    CpuPort funcPort;
116
117    bool snoopRangeSent;
118
119    class MemTestSenderState : public Packet::SenderState
120    {
121      public:
122        /** Constructor. */
123        MemTestSenderState(uint8_t *_data)
124            : data(_data)
125        { }
126
127        // Hold onto data pointer
128        uint8_t *data;
129    };
130
131    PacketPtr retryPkt;
132
133    bool accessRetry;
134
135    unsigned size;		// size of testing memory region
136
137    unsigned percentReads;	// target percentage of read accesses
138    unsigned percentFunctional;	// target percentage of functional accesses
139    unsigned percentUncacheable;
140
141    int id;
142
143    std::set<unsigned> outstandingAddrs;
144
145    unsigned blockSize;
146
147    Addr blockAddrMask;
148
149    Addr blockAddr(Addr addr)
150    {
151        return (addr & ~blockAddrMask);
152    }
153
154    Addr traceBlockAddr;
155
156    Addr baseAddr1;		// fix this to option
157    Addr baseAddr2;		// fix this to option
158    Addr uncacheAddr;
159
160    unsigned progressInterval;	// frequency of progress reports
161    Tick nextProgressMessage;	// access # for next progress report
162
163    unsigned percentSourceUnaligned;
164    unsigned percentDestUnaligned;
165
166    Tick noResponseCycles;
167
168    uint64_t numReads;
169    uint64_t maxLoads;
170
171    bool atomic;
172
173    Stats::Scalar<> numReadsStat;
174    Stats::Scalar<> numWritesStat;
175    Stats::Scalar<> numCopiesStat;
176
177    // called by MemCompleteEvent::process()
178    void completeRequest(PacketPtr pkt);
179
180    void sendPkt(PacketPtr pkt);
181
182    void doRetry();
183
184    friend class MemCompleteEvent;
185};
186
187#endif // __CPU_MEMTEST_MEMTEST_HH__
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