memtest.hh revision 5100 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Steve Reinhardt
30 */
31
32#ifndef __CPU_MEMTEST_MEMTEST_HH__
33#define __CPU_MEMTEST_MEMTEST_HH__
34
35#include <set>
36
37#include "base/statistics.hh"
38#include "params/MemTest.hh"
39#include "sim/eventq.hh"
40#include "sim/sim_exit.hh"
41#include "sim/sim_object.hh"
42#include "sim/stats.hh"
43#include "mem/mem_object.hh"
44#include "mem/port.hh"
45
46class Packet;
47class MemTest : public MemObject
48{
49  public:
50    typedef MemTestParams Params;
51    MemTest(const Params *p);
52
53    virtual void init();
54
55    // register statistics
56    virtual void regStats();
57
58    inline Tick ticks(int numCycles) const { return numCycles; }
59
60    // main simulation loop (one cycle)
61    void tick();
62
63    virtual Port *getPort(const std::string &if_name, int idx = -1);
64
65  protected:
66    class TickEvent : public Event
67    {
68      private:
69        MemTest *cpu;
70      public:
71        TickEvent(MemTest *c)
72            : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {}
73        void process() {cpu->tick();}
74        virtual const char *description() { return "MemTest tick"; }
75    };
76
77    TickEvent tickEvent;
78
79    class CpuPort : public Port
80    {
81        MemTest *memtest;
82
83      public:
84
85        CpuPort(const std::string &_name, MemTest *_memtest)
86            : Port(_name, _memtest), memtest(_memtest)
87        { }
88
89        bool snoopRangeSent;
90
91      protected:
92
93        virtual bool recvTiming(PacketPtr pkt);
94
95        virtual Tick recvAtomic(PacketPtr pkt);
96
97        virtual void recvFunctional(PacketPtr pkt);
98
99        virtual void recvStatusChange(Status status);
100
101        virtual void recvRetry();
102
103        virtual void getDeviceAddressRanges(AddrRangeList &resp,
104                                            bool &snoop)
105        { resp.clear(); snoop = false; }
106    };
107
108    CpuPort cachePort;
109    CpuPort funcPort;
110
111    bool snoopRangeSent;
112
113    class MemTestSenderState : public Packet::SenderState
114    {
115      public:
116        /** Constructor. */
117        MemTestSenderState(uint8_t *_data)
118            : data(_data)
119        { }
120
121        // Hold onto data pointer
122        uint8_t *data;
123    };
124
125    PacketPtr retryPkt;
126
127    bool accessRetry;
128
129    unsigned size;		// size of testing memory region
130
131    unsigned percentReads;	// target percentage of read accesses
132    unsigned percentFunctional;	// target percentage of functional accesses
133    unsigned percentUncacheable;
134
135    int id;
136
137    std::set<unsigned> outstandingAddrs;
138
139    unsigned blockSize;
140
141    Addr blockAddrMask;
142
143    Addr blockAddr(Addr addr)
144    {
145        return (addr & ~blockAddrMask);
146    }
147
148    Addr traceBlockAddr;
149
150    Addr baseAddr1;		// fix this to option
151    Addr baseAddr2;		// fix this to option
152    Addr uncacheAddr;
153
154    unsigned progressInterval;	// frequency of progress reports
155    Tick nextProgressMessage;	// access # for next progress report
156
157    unsigned percentSourceUnaligned;
158    unsigned percentDestUnaligned;
159
160    Tick noResponseCycles;
161
162    uint64_t numReads;
163    uint64_t maxLoads;
164
165    bool atomic;
166
167    Stats::Scalar<> numReadsStat;
168    Stats::Scalar<> numWritesStat;
169    Stats::Scalar<> numCopiesStat;
170
171    // called by MemCompleteEvent::process()
172    void completeRequest(PacketPtr pkt);
173
174    void sendPkt(PacketPtr pkt);
175
176    void doRetry();
177
178    friend class MemCompleteEvent;
179};
180
181#endif // __CPU_MEMTEST_MEMTEST_HH__
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