memtest.hh revision 2665 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Steve Reinhardt
30 */
31
32#ifndef __CPU_MEMTEST_MEMTEST_HH__
33#define __CPU_MEMTEST_MEMTEST_HH__
34
35#include <set>
36
37#include "base/statistics.hh"
38#include "mem/functional/functional.hh"
39#include "mem/mem_interface.hh"
40#include "sim/eventq.hh"
41#include "sim/sim_exit.hh"
42#include "sim/sim_object.hh"
43#include "sim/stats.hh"
44
45class ExecContext;
46class MemTest : public SimObject
47{
48  public:
49
50    MemTest(const std::string &name,
51            MemInterface *_cache_interface,
52            FunctionalMemory *main_mem,
53            FunctionalMemory *check_mem,
54            unsigned _memorySize,
55            unsigned _percentReads,
56            unsigned _percentCopies,
57            unsigned _percentUncacheable,
58            unsigned _progressInterval,
59            unsigned _percentSourceUnaligned,
60            unsigned _percentDestUnaligned,
61            Addr _traceAddr,
62            Counter _max_loads);
63
64    // register statistics
65    virtual void regStats();
66
67    inline Tick cycles(int numCycles) const { return numCycles; }
68
69    // main simulation loop (one cycle)
70    void tick();
71
72  protected:
73    class TickEvent : public Event
74    {
75      private:
76        MemTest *cpu;
77      public:
78        TickEvent(MemTest *c)
79            : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {}
80        void process() {cpu->tick();}
81        virtual const char *description() { return "tick event"; }
82    };
83
84    TickEvent tickEvent;
85
86    MemInterface *cacheInterface;
87    FunctionalMemory *mainMem;
88    FunctionalMemory *checkMem;
89    CPUExecContext *cpuXC;
90
91    unsigned size;		// size of testing memory region
92
93    unsigned percentReads;	// target percentage of read accesses
94    unsigned percentCopies;	// target percentage of copy accesses
95    unsigned percentUncacheable;
96
97    int id;
98
99    std::set<unsigned> outstandingAddrs;
100
101    unsigned blockSize;
102
103    Addr blockAddrMask;
104
105    Addr blockAddr(Addr addr)
106    {
107        return (addr & ~blockAddrMask);
108    }
109
110    Addr traceBlockAddr;
111
112    Addr baseAddr1;		// fix this to option
113    Addr baseAddr2;		// fix this to option
114    Addr uncacheAddr;
115
116    unsigned progressInterval;	// frequency of progress reports
117    Tick nextProgressMessage;	// access # for next progress report
118
119    unsigned percentSourceUnaligned;
120    unsigned percentDestUnaligned;
121
122    Tick noResponseCycles;
123
124    uint64_t numReads;
125    uint64_t maxLoads;
126    Stats::Scalar<> numReadsStat;
127    Stats::Scalar<> numWritesStat;
128    Stats::Scalar<> numCopiesStat;
129
130    // called by MemCompleteEvent::process()
131    void completeRequest(MemReqPtr &req, uint8_t *data);
132
133    friend class MemCompleteEvent;
134};
135
136
137class MemCompleteEvent : public Event
138{
139    MemReqPtr req;
140    uint8_t *data;
141    MemTest *tester;
142
143  public:
144
145    MemCompleteEvent(MemReqPtr &_req, uint8_t *_data, MemTest *_tester)
146        : Event(&mainEventQueue),
147          req(_req), data(_data), tester(_tester)
148    {
149    }
150
151    void process();
152
153    virtual const char *description();
154};
155
156#endif // __CPU_MEMTEST_MEMTEST_HH__
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