memtest.hh revision 1762 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_MEMTEST_MEMTEST_HH__
30#define __CPU_MEMTEST_MEMTEST_HH__
31
32#include <set>
33
34#include "base/statistics.hh"
35#include "mem/functional/functional.hh"
36#include "mem/mem_interface.hh"
37#include "sim/eventq.hh"
38#include "sim/sim_exit.hh"
39#include "sim/sim_object.hh"
40#include "sim/stats.hh"
41
42class ExecContext;
43class MemTest : public SimObject
44{
45  public:
46
47    MemTest(const std::string &name,
48            MemInterface *_cache_interface,
49            FunctionalMemory *main_mem,
50            FunctionalMemory *check_mem,
51            unsigned _memorySize,
52            unsigned _percentReads,
53            unsigned _percentCopies,
54            unsigned _percentUncacheable,
55            unsigned _progressInterval,
56            unsigned _percentSourceUnaligned,
57            unsigned _percentDestUnaligned,
58            Addr _traceAddr,
59            Counter _max_loads);
60
61    // register statistics
62    virtual void regStats();
63
64    inline Tick cycles(int numCycles) const { return numCycles; }
65
66    // main simulation loop (one cycle)
67    void tick();
68
69  protected:
70    class TickEvent : public Event
71    {
72      private:
73        MemTest *cpu;
74      public:
75        TickEvent(MemTest *c)
76            : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {}
77        void process() {cpu->tick();}
78        virtual const char *description() { return "tick event"; }
79    };
80
81    TickEvent tickEvent;
82
83    MemInterface *cacheInterface;
84    FunctionalMemory *mainMem;
85    FunctionalMemory *checkMem;
86    ExecContext *xc;
87
88    unsigned size;		// size of testing memory region
89
90    unsigned percentReads;	// target percentage of read accesses
91    unsigned percentCopies;	// target percentage of copy accesses
92    unsigned percentUncacheable;
93
94    int id;
95
96    std::set<unsigned> outstandingAddrs;
97
98    unsigned blockSize;
99
100    Addr blockAddrMask;
101
102    Addr blockAddr(Addr addr)
103    {
104        return (addr & ~blockAddrMask);
105    }
106
107    Addr traceBlockAddr;
108
109    Addr baseAddr1;		// fix this to option
110    Addr baseAddr2;		// fix this to option
111    Addr uncacheAddr;
112
113    unsigned progressInterval;	// frequency of progress reports
114    Tick nextProgressMessage;	// access # for next progress report
115
116    unsigned percentSourceUnaligned;
117    unsigned percentDestUnaligned;
118
119    Tick noResponseCycles;
120
121    uint64_t numReads;
122    uint64_t maxLoads;
123    Stats::Scalar<> numReadsStat;
124    Stats::Scalar<> numWritesStat;
125    Stats::Scalar<> numCopiesStat;
126
127    // called by MemCompleteEvent::process()
128    void completeRequest(MemReqPtr &req, uint8_t *data);
129
130    friend class MemCompleteEvent;
131};
132
133
134class MemCompleteEvent : public Event
135{
136    MemReqPtr req;
137    uint8_t *data;
138    MemTest *tester;
139
140  public:
141
142    MemCompleteEvent(MemReqPtr &_req, uint8_t *_data, MemTest *_tester)
143        : Event(&mainEventQueue),
144          req(_req), data(_data), tester(_tester)
145    {
146    }
147
148    void process();
149
150    virtual const char *description();
151};
152
153#endif // __CPU_MEMTEST_MEMTEST_HH__
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