memtest.hh revision 1634
111986Sandreas.sandberg@arm.com/* 211986Sandreas.sandberg@arm.com * Copyright (c) 2002-2004 The Regents of The University of Michigan 311986Sandreas.sandberg@arm.com * All rights reserved. 411986Sandreas.sandberg@arm.com * 511986Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 611986Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 711986Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 811986Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 911986Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1011986Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 1111986Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 1211986Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 1311986Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 1411986Sandreas.sandberg@arm.com * this software without specific prior written permission. 1511986Sandreas.sandberg@arm.com * 1611986Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711986Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811986Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912391Sjason@lowepower.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012391Sjason@lowepower.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112391Sjason@lowepower.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211986Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312391Sjason@lowepower.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411986Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511986Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611986Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711986Sandreas.sandberg@arm.com */ 2811986Sandreas.sandberg@arm.com 2911986Sandreas.sandberg@arm.com#ifndef __CPU_MEMTEST_MEMTEST_HH__ 3011986Sandreas.sandberg@arm.com#define __CPU_MEMTEST_MEMTEST_HH__ 3111986Sandreas.sandberg@arm.com 3211986Sandreas.sandberg@arm.com#include <set> 3311986Sandreas.sandberg@arm.com 3411986Sandreas.sandberg@arm.com#include "base/statistics.hh" 3512391Sjason@lowepower.com#include "mem/functional_mem/functional_memory.hh" 3612391Sjason@lowepower.com#include "mem/mem_interface.hh" 3712391Sjason@lowepower.com#include "sim/eventq.hh" 3811986Sandreas.sandberg@arm.com#include "sim/sim_exit.hh" 3912391Sjason@lowepower.com#include "sim/sim_object.hh" 4012391Sjason@lowepower.com#include "sim/stats.hh" 4111986Sandreas.sandberg@arm.com 4211986Sandreas.sandberg@arm.comclass ExecContext; 4311986Sandreas.sandberg@arm.comclass MemTest : public SimObject 4412037Sandreas.sandberg@arm.com{ 4512037Sandreas.sandberg@arm.com public: 4612391Sjason@lowepower.com 4712391Sjason@lowepower.com MemTest(const std::string &name, 4812391Sjason@lowepower.com MemInterface *_cache_interface, 4912391Sjason@lowepower.com FunctionalMemory *main_mem, 5012391Sjason@lowepower.com FunctionalMemory *check_mem, 5112391Sjason@lowepower.com unsigned _memorySize, 5212391Sjason@lowepower.com unsigned _percentReads, 5312391Sjason@lowepower.com unsigned _percentCopies, 5412391Sjason@lowepower.com unsigned _percentUncacheable, 5512391Sjason@lowepower.com unsigned _progressInterval, 5612391Sjason@lowepower.com unsigned _percentSourceUnaligned, 5712391Sjason@lowepower.com unsigned _percentDestUnaligned, 5812391Sjason@lowepower.com Addr _traceAddr, 5912391Sjason@lowepower.com Counter _max_loads); 6012391Sjason@lowepower.com 6112391Sjason@lowepower.com // register statistics 6212391Sjason@lowepower.com virtual void regStats(); 6312391Sjason@lowepower.com 6412391Sjason@lowepower.com inline Tick cycles(int numCycles) const { return numCycles; } 6512391Sjason@lowepower.com 6612391Sjason@lowepower.com // main simulation loop (one cycle) 6712391Sjason@lowepower.com void tick(); 6812391Sjason@lowepower.com 6912391Sjason@lowepower.com protected: 7012391Sjason@lowepower.com class TickEvent : public Event 7112391Sjason@lowepower.com { 7212391Sjason@lowepower.com private: 7312391Sjason@lowepower.com MemTest *cpu; 7412037Sandreas.sandberg@arm.com public: 7512037Sandreas.sandberg@arm.com TickEvent(MemTest *c) 7612037Sandreas.sandberg@arm.com : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {} 7712037Sandreas.sandberg@arm.com void process() {cpu->tick();} 7812037Sandreas.sandberg@arm.com virtual const char *description() { return "tick event"; } 7912037Sandreas.sandberg@arm.com }; 8012037Sandreas.sandberg@arm.com 8112037Sandreas.sandberg@arm.com TickEvent tickEvent; 8212037Sandreas.sandberg@arm.com 8312037Sandreas.sandberg@arm.com MemInterface *cacheInterface; 8412391Sjason@lowepower.com FunctionalMemory *mainMem; 8512391Sjason@lowepower.com FunctionalMemory *checkMem; 8612037Sandreas.sandberg@arm.com ExecContext *xc; 8712037Sandreas.sandberg@arm.com 8812037Sandreas.sandberg@arm.com unsigned size; // size of testing memory region 8912391Sjason@lowepower.com 90 unsigned percentReads; // target percentage of read accesses 91 unsigned percentCopies; // target percentage of copy accesses 92 unsigned percentUncacheable; 93 94 int id; 95 96 std::set<unsigned> outstandingAddrs; 97 98 unsigned blockSize; 99 100 Addr blockAddrMask; 101 102 Addr blockAddr(Addr addr) 103 { 104 return (addr & ~blockAddrMask); 105 } 106 107 Addr traceBlockAddr; 108 109 Addr baseAddr1; // fix this to option 110 Addr baseAddr2; // fix this to option 111 Addr uncacheAddr; 112 113 unsigned progressInterval; // frequency of progress reports 114 Tick nextProgressMessage; // access # for next progress report 115 116 unsigned percentSourceUnaligned; 117 unsigned percentDestUnaligned; 118 119 Tick noResponseCycles; 120 121 uint64_t numReads; 122 uint64_t maxLoads; 123 Stats::Scalar<> numReadsStat; 124 Stats::Scalar<> numWritesStat; 125 Stats::Scalar<> numCopiesStat; 126 127 // called by MemCompleteEvent::process() 128 void completeRequest(MemReqPtr &req, uint8_t *data); 129 130 friend class MemCompleteEvent; 131}; 132 133 134class MemCompleteEvent : public Event 135{ 136 MemReqPtr req; 137 uint8_t *data; 138 MemTest *tester; 139 140 public: 141 142 MemCompleteEvent(MemReqPtr &_req, uint8_t *_data, MemTest *_tester) 143 : Event(&mainEventQueue), 144 req(_req), data(_data), tester(_tester) 145 { 146 } 147 148 void process(); 149 150 virtual const char *description(); 151}; 152 153#endif // __CPU_MEMTEST_MEMTEST_HH__ 154 155 156 157