memtest.cc revision 9814:7ad2b0186a32 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Steve Reinhardt
30 */
31
32// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
33
34#include <iomanip>
35#include <set>
36#include <string>
37#include <vector>
38
39#include "base/misc.hh"
40#include "base/statistics.hh"
41#include "cpu/testers/memtest/memtest.hh"
42#include "debug/MemTest.hh"
43#include "mem/mem_object.hh"
44#include "mem/packet.hh"
45#include "mem/port.hh"
46#include "mem/request.hh"
47#include "sim/sim_events.hh"
48#include "sim/stats.hh"
49#include "sim/system.hh"
50
51using namespace std;
52
53int TESTER_ALLOCATOR=0;
54
55bool
56MemTest::CpuPort::recvTimingResp(PacketPtr pkt)
57{
58    memtest->completeRequest(pkt);
59    return true;
60}
61
62void
63MemTest::CpuPort::recvRetry()
64{
65    memtest->doRetry();
66}
67
68void
69MemTest::sendPkt(PacketPtr pkt) {
70    if (atomic) {
71        cachePort.sendAtomic(pkt);
72        completeRequest(pkt);
73    }
74    else if (!cachePort.sendTimingReq(pkt)) {
75        DPRINTF(MemTest, "accessRetry setting to true\n");
76
77        //
78        // dma requests should never be retried
79        //
80        if (issueDmas) {
81            panic("Nacked DMA requests are not supported\n");
82        }
83        accessRetry = true;
84        retryPkt = pkt;
85    } else {
86        if (issueDmas) {
87            dmaOutstanding = true;
88        }
89    }
90
91}
92
93MemTest::MemTest(const Params *p)
94    : MemObject(p),
95      tickEvent(this),
96      cachePort("test", this),
97      funcPort("functional", this),
98      funcProxy(funcPort, p->sys->cacheLineSize()),
99      retryPkt(NULL),
100//      mainMem(main_mem),
101//      checkMem(check_mem),
102      size(p->memory_size),
103      percentReads(p->percent_reads),
104      percentFunctional(p->percent_functional),
105      percentUncacheable(p->percent_uncacheable),
106      issueDmas(p->issue_dmas),
107      masterId(p->sys->getMasterId(name())),
108      blockSize(p->sys->cacheLineSize()),
109      progressInterval(p->progress_interval),
110      nextProgressMessage(p->progress_interval),
111      percentSourceUnaligned(p->percent_source_unaligned),
112      percentDestUnaligned(p->percent_dest_unaligned),
113      maxLoads(p->max_loads),
114      atomic(p->atomic),
115      suppress_func_warnings(p->suppress_func_warnings)
116{
117    id = TESTER_ALLOCATOR++;
118
119    // Needs to be masked off once we know the block size.
120    traceBlockAddr = p->trace_addr;
121    baseAddr1 = 0x100000;
122    baseAddr2 = 0x400000;
123    uncacheAddr = 0x800000;
124
125    blockAddrMask = blockSize - 1;
126    traceBlockAddr = blockAddr(traceBlockAddr);
127
128    // set up counters
129    noResponseCycles = 0;
130    numReads = 0;
131    numWrites = 0;
132    schedule(tickEvent, 0);
133
134    accessRetry = false;
135    dmaOutstanding = false;
136}
137
138BaseMasterPort &
139MemTest::getMasterPort(const std::string &if_name, PortID idx)
140{
141    if (if_name == "functional")
142        return funcPort;
143    else if (if_name == "test")
144        return cachePort;
145    else
146        return MemObject::getMasterPort(if_name, idx);
147}
148
149void
150MemTest::init()
151{
152    // initial memory contents for both physical memory and functional
153    // memory should be 0; no need to initialize them.
154}
155
156
157void
158MemTest::completeRequest(PacketPtr pkt)
159{
160    Request *req = pkt->req;
161
162    if (issueDmas) {
163        dmaOutstanding = false;
164    }
165
166    DPRINTF(MemTest, "completing %s at address %x (blk %x) %s\n",
167            pkt->isWrite() ? "write" : "read",
168            req->getPaddr(), blockAddr(req->getPaddr()),
169            pkt->isError() ? "error" : "success");
170
171    MemTestSenderState *state =
172        dynamic_cast<MemTestSenderState *>(pkt->senderState);
173
174    uint8_t *data = state->data;
175    uint8_t *pkt_data = pkt->getPtr<uint8_t>();
176
177    //Remove the address from the list of outstanding
178    std::set<unsigned>::iterator removeAddr =
179        outstandingAddrs.find(req->getPaddr());
180    assert(removeAddr != outstandingAddrs.end());
181    outstandingAddrs.erase(removeAddr);
182
183    if (pkt->isError()) {
184        if (!suppress_func_warnings) {
185          warn("Functional %s access failed at %#x\n",
186               pkt->isWrite() ? "write" : "read", req->getPaddr());
187        }
188    } else {
189        if (pkt->isRead()) {
190            if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
191                panic("%s: read of %x (blk %x) @ cycle %d "
192                      "returns %x, expected %x\n", name(),
193                      req->getPaddr(), blockAddr(req->getPaddr()), curTick(),
194                      *pkt_data, *data);
195            }
196
197            numReads++;
198            numReadsStat++;
199
200            if (numReads == (uint64_t)nextProgressMessage) {
201                ccprintf(cerr, "%s: completed %d read, %d write accesses @%d\n",
202                         name(), numReads, numWrites, curTick());
203                nextProgressMessage += progressInterval;
204            }
205
206            if (maxLoads != 0 && numReads >= maxLoads)
207                exitSimLoop("maximum number of loads reached");
208        } else {
209            assert(pkt->isWrite());
210            funcProxy.writeBlob(req->getPaddr(), pkt_data, req->getSize());
211            numWrites++;
212            numWritesStat++;
213        }
214    }
215
216    noResponseCycles = 0;
217    delete state;
218    delete [] data;
219    delete pkt->req;
220    delete pkt;
221}
222
223void
224MemTest::regStats()
225{
226    using namespace Stats;
227
228    numReadsStat
229        .name(name() + ".num_reads")
230        .desc("number of read accesses completed")
231        ;
232
233    numWritesStat
234        .name(name() + ".num_writes")
235        .desc("number of write accesses completed")
236        ;
237
238    numCopiesStat
239        .name(name() + ".num_copies")
240        .desc("number of copy accesses completed")
241        ;
242}
243
244void
245MemTest::tick()
246{
247    if (!tickEvent.scheduled())
248        schedule(tickEvent, clockEdge(Cycles(1)));
249
250    if (++noResponseCycles >= 500000) {
251        if (issueDmas) {
252            cerr << "DMA tester ";
253        }
254        cerr << name() << ": deadlocked at cycle " << curTick() << endl;
255        fatal("");
256    }
257
258    if (accessRetry || (issueDmas && dmaOutstanding)) {
259        DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n");
260        return;
261    }
262
263    //make new request
264    unsigned cmd = random() % 100;
265    unsigned offset = random() % size;
266    unsigned base = random() % 2;
267    uint64_t data = random();
268    unsigned access_size = random() % 4;
269    bool uncacheable = (random() % 100) < percentUncacheable;
270
271    unsigned dma_access_size = random() % 4;
272
273    //If we aren't doing copies, use id as offset, and do a false sharing
274    //mem tester
275    //We can eliminate the lower bits of the offset, and then use the id
276    //to offset within the blks
277    offset = blockAddr(offset);
278    offset += id;
279    access_size = 0;
280    dma_access_size = 0;
281
282    Request::Flags flags;
283    Addr paddr;
284
285    if (uncacheable) {
286        flags.set(Request::UNCACHEABLE);
287        paddr = uncacheAddr + offset;
288    } else  {
289        paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
290    }
291
292    // For now we only allow one outstanding request per address
293    // per tester This means we assume CPU does write forwarding
294    // to reads that alias something in the cpu store buffer.
295    if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
296        return;
297    }
298
299    bool do_functional = (random() % 100 < percentFunctional) && !uncacheable;
300    Request *req = new Request();
301    uint8_t *result = new uint8_t[8];
302
303    if (issueDmas) {
304        paddr &= ~((1 << dma_access_size) - 1);
305        req->setPhys(paddr, 1 << dma_access_size, flags, masterId);
306        req->setThreadContext(id,0);
307    } else {
308        paddr &= ~((1 << access_size) - 1);
309        req->setPhys(paddr, 1 << access_size, flags, masterId);
310        req->setThreadContext(id,0);
311    }
312    assert(req->getSize() == 1);
313
314    if (cmd < percentReads) {
315        // read
316        outstandingAddrs.insert(paddr);
317
318        // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
319        funcProxy.readBlob(req->getPaddr(), result, req->getSize());
320
321        DPRINTF(MemTest,
322                "id %d initiating %sread at addr %x (blk %x) expecting %x\n",
323                id, do_functional ? "functional " : "", req->getPaddr(),
324                blockAddr(req->getPaddr()), *result);
325
326        PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
327        pkt->dataDynamicArray(new uint8_t[req->getSize()]);
328        MemTestSenderState *state = new MemTestSenderState(result);
329        pkt->senderState = state;
330
331        if (do_functional) {
332            assert(pkt->needsResponse());
333            pkt->setSuppressFuncError();
334            cachePort.sendFunctional(pkt);
335            completeRequest(pkt);
336        } else {
337            sendPkt(pkt);
338        }
339    } else {
340        // write
341        outstandingAddrs.insert(paddr);
342
343        DPRINTF(MemTest, "initiating %swrite at addr %x (blk %x) value %x\n",
344                do_functional ? "functional " : "", req->getPaddr(),
345                blockAddr(req->getPaddr()), data & 0xff);
346
347        PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
348        uint8_t *pkt_data = new uint8_t[req->getSize()];
349        pkt->dataDynamicArray(pkt_data);
350        memcpy(pkt_data, &data, req->getSize());
351        MemTestSenderState *state = new MemTestSenderState(result);
352        pkt->senderState = state;
353
354        if (do_functional) {
355            pkt->setSuppressFuncError();
356            cachePort.sendFunctional(pkt);
357            completeRequest(pkt);
358        } else {
359            sendPkt(pkt);
360        }
361    }
362}
363
364void
365MemTest::doRetry()
366{
367    if (cachePort.sendTimingReq(retryPkt)) {
368        DPRINTF(MemTest, "accessRetry setting to false\n");
369        accessRetry = false;
370        retryPkt = NULL;
371    }
372}
373
374
375void
376MemTest::printAddr(Addr a)
377{
378    cachePort.printAddr(a);
379}
380
381
382MemTest *
383MemTestParams::create()
384{
385    return new MemTest(this);
386}
387