memtest.cc revision 8949:3fa1ee293096 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Steve Reinhardt
30 */
31
32// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
33
34#include <iomanip>
35#include <set>
36#include <string>
37#include <vector>
38
39#include "base/misc.hh"
40#include "base/statistics.hh"
41#include "cpu/testers/memtest/memtest.hh"
42#include "debug/MemTest.hh"
43#include "mem/mem_object.hh"
44#include "mem/packet.hh"
45#include "mem/port.hh"
46#include "mem/request.hh"
47#include "sim/sim_events.hh"
48#include "sim/stats.hh"
49#include "sim/system.hh"
50
51using namespace std;
52
53int TESTER_ALLOCATOR=0;
54
55bool
56MemTest::CpuPort::recvTiming(PacketPtr pkt)
57{
58    assert(pkt->isResponse());
59    memtest->completeRequest(pkt);
60    return true;
61}
62
63void
64MemTest::CpuPort::recvRetry()
65{
66    memtest->doRetry();
67}
68
69void
70MemTest::sendPkt(PacketPtr pkt) {
71    if (atomic) {
72        cachePort.sendAtomic(pkt);
73        completeRequest(pkt);
74    }
75    else if (!cachePort.sendTiming(pkt)) {
76        DPRINTF(MemTest, "accessRetry setting to true\n");
77
78        //
79        // dma requests should never be retried
80        //
81        if (issueDmas) {
82            panic("Nacked DMA requests are not supported\n");
83        }
84        accessRetry = true;
85        retryPkt = pkt;
86    } else {
87        if (issueDmas) {
88            dmaOutstanding = true;
89        }
90    }
91
92}
93
94MemTest::MemTest(const Params *p)
95    : MemObject(p),
96      tickEvent(this),
97      cachePort("test", this),
98      funcPort("functional", this),
99      funcProxy(funcPort),
100      retryPkt(NULL),
101//      mainMem(main_mem),
102//      checkMem(check_mem),
103      size(p->memory_size),
104      percentReads(p->percent_reads),
105      percentFunctional(p->percent_functional),
106      percentUncacheable(p->percent_uncacheable),
107      issueDmas(p->issue_dmas),
108      masterId(p->sys->getMasterId(name())),
109      progressInterval(p->progress_interval),
110      nextProgressMessage(p->progress_interval),
111      percentSourceUnaligned(p->percent_source_unaligned),
112      percentDestUnaligned(p->percent_dest_unaligned),
113      maxLoads(p->max_loads),
114      atomic(p->atomic),
115      suppress_func_warnings(p->suppress_func_warnings)
116{
117    id = TESTER_ALLOCATOR++;
118
119    // Needs to be masked off once we know the block size.
120    traceBlockAddr = p->trace_addr;
121    baseAddr1 = 0x100000;
122    baseAddr2 = 0x400000;
123    uncacheAddr = 0x800000;
124
125    // set up counters
126    noResponseCycles = 0;
127    numReads = 0;
128    numWrites = 0;
129    schedule(tickEvent, 0);
130
131    accessRetry = false;
132    dmaOutstanding = false;
133}
134
135MasterPort &
136MemTest::getMasterPort(const std::string &if_name, int idx)
137{
138    if (if_name == "functional")
139        return funcPort;
140    else if (if_name == "test")
141        return cachePort;
142    else
143        return MemObject::getMasterPort(if_name, idx);
144}
145
146void
147MemTest::init()
148{
149    // By the time init() is called, the ports should be hooked up.
150    blockSize = cachePort.peerBlockSize();
151    blockAddrMask = blockSize - 1;
152    traceBlockAddr = blockAddr(traceBlockAddr);
153
154    // initial memory contents for both physical memory and functional
155    // memory should be 0; no need to initialize them.
156}
157
158
159void
160MemTest::completeRequest(PacketPtr pkt)
161{
162    Request *req = pkt->req;
163
164    if (issueDmas) {
165        dmaOutstanding = false;
166    }
167
168    DPRINTF(MemTest, "completing %s at address %x (blk %x) %s\n",
169            pkt->isWrite() ? "write" : "read",
170            req->getPaddr(), blockAddr(req->getPaddr()),
171            pkt->isError() ? "error" : "success");
172
173    MemTestSenderState *state =
174        dynamic_cast<MemTestSenderState *>(pkt->senderState);
175
176    uint8_t *data = state->data;
177    uint8_t *pkt_data = pkt->getPtr<uint8_t>();
178
179    //Remove the address from the list of outstanding
180    std::set<unsigned>::iterator removeAddr =
181        outstandingAddrs.find(req->getPaddr());
182    assert(removeAddr != outstandingAddrs.end());
183    outstandingAddrs.erase(removeAddr);
184
185    if (pkt->isError()) {
186        if (!suppress_func_warnings) {
187          warn("Functional Access failed for %x at %x\n",
188               pkt->isWrite() ? "write" : "read", req->getPaddr());
189        }
190    } else {
191        if (pkt->isRead()) {
192            if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
193                panic("%s: read of %x (blk %x) @ cycle %d "
194                      "returns %x, expected %x\n", name(),
195                      req->getPaddr(), blockAddr(req->getPaddr()), curTick(),
196                      *pkt_data, *data);
197            }
198
199            numReads++;
200            numReadsStat++;
201
202            if (numReads == (uint64_t)nextProgressMessage) {
203                ccprintf(cerr, "%s: completed %d read, %d write accesses @%d\n",
204                         name(), numReads, numWrites, curTick());
205                nextProgressMessage += progressInterval;
206            }
207
208            if (maxLoads != 0 && numReads >= maxLoads)
209                exitSimLoop("maximum number of loads reached");
210        } else {
211            assert(pkt->isWrite());
212            funcProxy.writeBlob(req->getPaddr(), pkt_data, req->getSize());
213            numWrites++;
214            numWritesStat++;
215        }
216    }
217
218    noResponseCycles = 0;
219    delete state;
220    delete [] data;
221    delete pkt->req;
222    delete pkt;
223}
224
225void
226MemTest::regStats()
227{
228    using namespace Stats;
229
230    numReadsStat
231        .name(name() + ".num_reads")
232        .desc("number of read accesses completed")
233        ;
234
235    numWritesStat
236        .name(name() + ".num_writes")
237        .desc("number of write accesses completed")
238        ;
239
240    numCopiesStat
241        .name(name() + ".num_copies")
242        .desc("number of copy accesses completed")
243        ;
244}
245
246void
247MemTest::tick()
248{
249    if (!tickEvent.scheduled())
250        schedule(tickEvent, curTick() + ticks(1));
251
252    if (++noResponseCycles >= 500000) {
253        if (issueDmas) {
254            cerr << "DMA tester ";
255        }
256        cerr << name() << ": deadlocked at cycle " << curTick() << endl;
257        fatal("");
258    }
259
260    if (accessRetry || (issueDmas && dmaOutstanding)) {
261        DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n");
262        return;
263    }
264
265    //make new request
266    unsigned cmd = random() % 100;
267    unsigned offset = random() % size;
268    unsigned base = random() % 2;
269    uint64_t data = random();
270    unsigned access_size = random() % 4;
271    bool uncacheable = (random() % 100) < percentUncacheable;
272
273    unsigned dma_access_size = random() % 4;
274
275    //If we aren't doing copies, use id as offset, and do a false sharing
276    //mem tester
277    //We can eliminate the lower bits of the offset, and then use the id
278    //to offset within the blks
279    offset = blockAddr(offset);
280    offset += id;
281    access_size = 0;
282    dma_access_size = 0;
283
284    Request *req = new Request();
285    Request::Flags flags;
286    Addr paddr;
287
288    if (uncacheable) {
289        flags.set(Request::UNCACHEABLE);
290        paddr = uncacheAddr + offset;
291    } else  {
292        paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
293    }
294    bool do_functional = (random() % 100 < percentFunctional) && !uncacheable;
295
296    if (issueDmas) {
297        paddr &= ~((1 << dma_access_size) - 1);
298        req->setPhys(paddr, 1 << dma_access_size, flags, masterId);
299        req->setThreadContext(id,0);
300    } else {
301        paddr &= ~((1 << access_size) - 1);
302        req->setPhys(paddr, 1 << access_size, flags, masterId);
303        req->setThreadContext(id,0);
304    }
305    assert(req->getSize() == 1);
306
307    uint8_t *result = new uint8_t[8];
308
309    if (cmd < percentReads) {
310        // read
311
312        // For now we only allow one outstanding request per address
313        // per tester This means we assume CPU does write forwarding
314        // to reads that alias something in the cpu store buffer.
315        if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
316            delete [] result;
317            delete req;
318            return;
319        }
320
321        outstandingAddrs.insert(paddr);
322
323        // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
324        funcProxy.readBlob(req->getPaddr(), result, req->getSize());
325
326        DPRINTF(MemTest,
327                "id %d initiating %sread at addr %x (blk %x) expecting %x\n",
328                id, do_functional ? "functional " : "", req->getPaddr(),
329                blockAddr(req->getPaddr()), *result);
330
331        PacketPtr pkt = new Packet(req, MemCmd::ReadReq);
332        pkt->dataDynamicArray(new uint8_t[req->getSize()]);
333        MemTestSenderState *state = new MemTestSenderState(result);
334        pkt->senderState = state;
335
336        if (do_functional) {
337            assert(pkt->needsResponse());
338            pkt->setSuppressFuncError();
339            cachePort.sendFunctional(pkt);
340            completeRequest(pkt);
341        } else {
342            sendPkt(pkt);
343        }
344    } else {
345        // write
346
347        // For now we only allow one outstanding request per addreess
348        // per tester.  This means we assume CPU does write forwarding
349        // to reads that alias something in the cpu store buffer.
350        if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
351            delete [] result;
352            delete req;
353            return;
354        }
355
356        outstandingAddrs.insert(paddr);
357
358        DPRINTF(MemTest, "initiating %swrite at addr %x (blk %x) value %x\n",
359                do_functional ? "functional " : "", req->getPaddr(),
360                blockAddr(req->getPaddr()), data & 0xff);
361
362        PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
363        uint8_t *pkt_data = new uint8_t[req->getSize()];
364        pkt->dataDynamicArray(pkt_data);
365        memcpy(pkt_data, &data, req->getSize());
366        MemTestSenderState *state = new MemTestSenderState(result);
367        pkt->senderState = state;
368
369        if (do_functional) {
370            pkt->setSuppressFuncError();
371            cachePort.sendFunctional(pkt);
372            completeRequest(pkt);
373        } else {
374            sendPkt(pkt);
375        }
376    }
377}
378
379void
380MemTest::doRetry()
381{
382    if (cachePort.sendTiming(retryPkt)) {
383        DPRINTF(MemTest, "accessRetry setting to false\n");
384        accessRetry = false;
385        retryPkt = NULL;
386    }
387}
388
389
390void
391MemTest::printAddr(Addr a)
392{
393    cachePort.printAddr(a);
394}
395
396
397MemTest *
398MemTestParams::create()
399{
400    return new MemTest(this);
401}
402