memtest.cc revision 8922:17f037ad8918 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Steve Reinhardt
30 */
31
32// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
33
34#include <iomanip>
35#include <set>
36#include <string>
37#include <vector>
38
39#include "base/misc.hh"
40#include "base/statistics.hh"
41#include "cpu/testers/memtest/memtest.hh"
42#include "debug/MemTest.hh"
43#include "mem/mem_object.hh"
44#include "mem/packet.hh"
45#include "mem/port.hh"
46#include "mem/request.hh"
47#include "sim/sim_events.hh"
48#include "sim/stats.hh"
49#include "sim/system.hh"
50
51using namespace std;
52
53int TESTER_ALLOCATOR=0;
54
55bool
56MemTest::CpuPort::recvTiming(PacketPtr pkt)
57{
58    if (pkt->isResponse()) {
59        memtest->completeRequest(pkt);
60    } else {
61        // must be snoop upcall
62        assert(pkt->isRequest());
63        assert(pkt->getDest() == Packet::Broadcast);
64    }
65    return true;
66}
67
68Tick
69MemTest::CpuPort::recvAtomic(PacketPtr pkt)
70{
71    // must be snoop upcall
72    assert(pkt->isRequest());
73    assert(pkt->getDest() == Packet::Broadcast);
74    return curTick();
75}
76
77void
78MemTest::CpuPort::recvFunctional(PacketPtr pkt)
79{
80    //Do nothing if we see one come through
81//    if (curTick() != 0)//Supress warning durring initialization
82//        warn("Functional Writes not implemented in MemTester\n");
83    //Need to find any response values that intersect and update
84    return;
85}
86
87void
88MemTest::CpuPort::recvRetry()
89{
90    memtest->doRetry();
91}
92
93void
94MemTest::sendPkt(PacketPtr pkt) {
95    if (atomic) {
96        cachePort.sendAtomic(pkt);
97        completeRequest(pkt);
98    }
99    else if (!cachePort.sendTiming(pkt)) {
100        DPRINTF(MemTest, "accessRetry setting to true\n");
101
102        //
103        // dma requests should never be retried
104        //
105        if (issueDmas) {
106            panic("Nacked DMA requests are not supported\n");
107        }
108        accessRetry = true;
109        retryPkt = pkt;
110    } else {
111        if (issueDmas) {
112            dmaOutstanding = true;
113        }
114    }
115
116}
117
118MemTest::MemTest(const Params *p)
119    : MemObject(p),
120      tickEvent(this),
121      cachePort("test", this),
122      funcPort("functional", this),
123      funcProxy(funcPort),
124      retryPkt(NULL),
125//      mainMem(main_mem),
126//      checkMem(check_mem),
127      size(p->memory_size),
128      percentReads(p->percent_reads),
129      percentFunctional(p->percent_functional),
130      percentUncacheable(p->percent_uncacheable),
131      issueDmas(p->issue_dmas),
132      masterId(p->sys->getMasterId(name())),
133      progressInterval(p->progress_interval),
134      nextProgressMessage(p->progress_interval),
135      percentSourceUnaligned(p->percent_source_unaligned),
136      percentDestUnaligned(p->percent_dest_unaligned),
137      maxLoads(p->max_loads),
138      atomic(p->atomic),
139      suppress_func_warnings(p->suppress_func_warnings)
140{
141    id = TESTER_ALLOCATOR++;
142
143    // Needs to be masked off once we know the block size.
144    traceBlockAddr = p->trace_addr;
145    baseAddr1 = 0x100000;
146    baseAddr2 = 0x400000;
147    uncacheAddr = 0x800000;
148
149    // set up counters
150    noResponseCycles = 0;
151    numReads = 0;
152    numWrites = 0;
153    schedule(tickEvent, 0);
154
155    accessRetry = false;
156    dmaOutstanding = false;
157}
158
159MasterPort &
160MemTest::getMasterPort(const std::string &if_name, int idx)
161{
162    if (if_name == "functional")
163        return funcPort;
164    else if (if_name == "test")
165        return cachePort;
166    else
167        return MemObject::getMasterPort(if_name, idx);
168}
169
170void
171MemTest::init()
172{
173    // By the time init() is called, the ports should be hooked up.
174    blockSize = cachePort.peerBlockSize();
175    blockAddrMask = blockSize - 1;
176    traceBlockAddr = blockAddr(traceBlockAddr);
177
178    // initial memory contents for both physical memory and functional
179    // memory should be 0; no need to initialize them.
180}
181
182
183void
184MemTest::completeRequest(PacketPtr pkt)
185{
186    Request *req = pkt->req;
187
188    if (issueDmas) {
189        dmaOutstanding = false;
190    }
191
192    DPRINTF(MemTest, "completing %s at address %x (blk %x) %s\n",
193            pkt->isWrite() ? "write" : "read",
194            req->getPaddr(), blockAddr(req->getPaddr()),
195            pkt->isError() ? "error" : "success");
196
197    MemTestSenderState *state =
198        dynamic_cast<MemTestSenderState *>(pkt->senderState);
199
200    uint8_t *data = state->data;
201    uint8_t *pkt_data = pkt->getPtr<uint8_t>();
202
203    //Remove the address from the list of outstanding
204    std::set<unsigned>::iterator removeAddr =
205        outstandingAddrs.find(req->getPaddr());
206    assert(removeAddr != outstandingAddrs.end());
207    outstandingAddrs.erase(removeAddr);
208
209    if (pkt->isError()) {
210        if (!suppress_func_warnings) {
211          warn("Functional Access failed for %x at %x\n",
212               pkt->isWrite() ? "write" : "read", req->getPaddr());
213        }
214    } else {
215        if (pkt->isRead()) {
216            if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
217                panic("%s: read of %x (blk %x) @ cycle %d "
218                      "returns %x, expected %x\n", name(),
219                      req->getPaddr(), blockAddr(req->getPaddr()), curTick(),
220                      *pkt_data, *data);
221            }
222
223            numReads++;
224            numReadsStat++;
225
226            if (numReads == (uint64_t)nextProgressMessage) {
227                ccprintf(cerr, "%s: completed %d read, %d write accesses @%d\n",
228                         name(), numReads, numWrites, curTick());
229                nextProgressMessage += progressInterval;
230            }
231
232            if (maxLoads != 0 && numReads >= maxLoads)
233                exitSimLoop("maximum number of loads reached");
234        } else {
235            assert(pkt->isWrite());
236            funcProxy.writeBlob(req->getPaddr(), pkt_data, req->getSize());
237            numWrites++;
238            numWritesStat++;
239        }
240    }
241
242    noResponseCycles = 0;
243    delete state;
244    delete [] data;
245    delete pkt->req;
246    delete pkt;
247}
248
249void
250MemTest::regStats()
251{
252    using namespace Stats;
253
254    numReadsStat
255        .name(name() + ".num_reads")
256        .desc("number of read accesses completed")
257        ;
258
259    numWritesStat
260        .name(name() + ".num_writes")
261        .desc("number of write accesses completed")
262        ;
263
264    numCopiesStat
265        .name(name() + ".num_copies")
266        .desc("number of copy accesses completed")
267        ;
268}
269
270void
271MemTest::tick()
272{
273    if (!tickEvent.scheduled())
274        schedule(tickEvent, curTick() + ticks(1));
275
276    if (++noResponseCycles >= 500000) {
277        if (issueDmas) {
278            cerr << "DMA tester ";
279        }
280        cerr << name() << ": deadlocked at cycle " << curTick() << endl;
281        fatal("");
282    }
283
284    if (accessRetry || (issueDmas && dmaOutstanding)) {
285        DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n");
286        return;
287    }
288
289    //make new request
290    unsigned cmd = random() % 100;
291    unsigned offset = random() % size;
292    unsigned base = random() % 2;
293    uint64_t data = random();
294    unsigned access_size = random() % 4;
295    bool uncacheable = (random() % 100) < percentUncacheable;
296
297    unsigned dma_access_size = random() % 4;
298
299    //If we aren't doing copies, use id as offset, and do a false sharing
300    //mem tester
301    //We can eliminate the lower bits of the offset, and then use the id
302    //to offset within the blks
303    offset = blockAddr(offset);
304    offset += id;
305    access_size = 0;
306    dma_access_size = 0;
307
308    Request *req = new Request();
309    Request::Flags flags;
310    Addr paddr;
311
312    if (uncacheable) {
313        flags.set(Request::UNCACHEABLE);
314        paddr = uncacheAddr + offset;
315    } else  {
316        paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
317    }
318    bool do_functional = (random() % 100 < percentFunctional) && !uncacheable;
319
320    if (issueDmas) {
321        paddr &= ~((1 << dma_access_size) - 1);
322        req->setPhys(paddr, 1 << dma_access_size, flags, masterId);
323        req->setThreadContext(id,0);
324    } else {
325        paddr &= ~((1 << access_size) - 1);
326        req->setPhys(paddr, 1 << access_size, flags, masterId);
327        req->setThreadContext(id,0);
328    }
329    assert(req->getSize() == 1);
330
331    uint8_t *result = new uint8_t[8];
332
333    if (cmd < percentReads) {
334        // read
335
336        // For now we only allow one outstanding request per address
337        // per tester This means we assume CPU does write forwarding
338        // to reads that alias something in the cpu store buffer.
339        if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
340            delete [] result;
341            delete req;
342            return;
343        }
344
345        outstandingAddrs.insert(paddr);
346
347        // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
348        funcProxy.readBlob(req->getPaddr(), result, req->getSize());
349
350        DPRINTF(MemTest,
351                "id %d initiating %sread at addr %x (blk %x) expecting %x\n",
352                id, do_functional ? "functional " : "", req->getPaddr(),
353                blockAddr(req->getPaddr()), *result);
354
355        PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
356        pkt->setSrc(0);
357        pkt->dataDynamicArray(new uint8_t[req->getSize()]);
358        MemTestSenderState *state = new MemTestSenderState(result);
359        pkt->senderState = state;
360
361        if (do_functional) {
362            assert(pkt->needsResponse());
363            pkt->setSuppressFuncError();
364            cachePort.sendFunctional(pkt);
365            completeRequest(pkt);
366        } else {
367            sendPkt(pkt);
368        }
369    } else {
370        // write
371
372        // For now we only allow one outstanding request per addreess
373        // per tester.  This means we assume CPU does write forwarding
374        // to reads that alias something in the cpu store buffer.
375        if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
376            delete [] result;
377            delete req;
378            return;
379        }
380
381        outstandingAddrs.insert(paddr);
382
383        DPRINTF(MemTest, "initiating %swrite at addr %x (blk %x) value %x\n",
384                do_functional ? "functional " : "", req->getPaddr(),
385                blockAddr(req->getPaddr()), data & 0xff);
386
387        PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
388        pkt->setSrc(0);
389        uint8_t *pkt_data = new uint8_t[req->getSize()];
390        pkt->dataDynamicArray(pkt_data);
391        memcpy(pkt_data, &data, req->getSize());
392        MemTestSenderState *state = new MemTestSenderState(result);
393        pkt->senderState = state;
394
395        if (do_functional) {
396            pkt->setSuppressFuncError();
397            cachePort.sendFunctional(pkt);
398            completeRequest(pkt);
399        } else {
400            sendPkt(pkt);
401        }
402    }
403}
404
405void
406MemTest::doRetry()
407{
408    if (cachePort.sendTiming(retryPkt)) {
409        DPRINTF(MemTest, "accessRetry setting to false\n");
410        accessRetry = false;
411        retryPkt = NULL;
412    }
413}
414
415
416void
417MemTest::printAddr(Addr a)
418{
419    cachePort.printAddr(a);
420}
421
422
423MemTest *
424MemTestParams::create()
425{
426    return new MemTest(this);
427}
428