memtest.cc revision 8232:b28d06a175be 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Steve Reinhardt
30 */
31
32// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
33
34#include <iomanip>
35#include <set>
36#include <string>
37#include <vector>
38
39#include "base/misc.hh"
40#include "base/statistics.hh"
41#include "cpu/testers/memtest/memtest.hh"
42#include "debug/MemTest.hh"
43#include "mem/mem_object.hh"
44#include "mem/packet.hh"
45#include "mem/port.hh"
46#include "mem/request.hh"
47#include "sim/sim_events.hh"
48#include "sim/stats.hh"
49
50using namespace std;
51
52int TESTER_ALLOCATOR=0;
53
54bool
55MemTest::CpuPort::recvTiming(PacketPtr pkt)
56{
57    if (pkt->isResponse()) {
58        memtest->completeRequest(pkt);
59    } else {
60        // must be snoop upcall
61        assert(pkt->isRequest());
62        assert(pkt->getDest() == Packet::Broadcast);
63    }
64    return true;
65}
66
67Tick
68MemTest::CpuPort::recvAtomic(PacketPtr pkt)
69{
70    // must be snoop upcall
71    assert(pkt->isRequest());
72    assert(pkt->getDest() == Packet::Broadcast);
73    return curTick();
74}
75
76void
77MemTest::CpuPort::recvFunctional(PacketPtr pkt)
78{
79    //Do nothing if we see one come through
80//    if (curTick() != 0)//Supress warning durring initialization
81//        warn("Functional Writes not implemented in MemTester\n");
82    //Need to find any response values that intersect and update
83    return;
84}
85
86void
87MemTest::CpuPort::recvStatusChange(Status status)
88{
89    if (status == RangeChange) {
90        if (!snoopRangeSent) {
91            snoopRangeSent = true;
92            sendStatusChange(Port::RangeChange);
93        }
94        return;
95    }
96
97    panic("MemTest doesn't expect recvStatusChange callback!");
98}
99
100void
101MemTest::CpuPort::recvRetry()
102{
103    memtest->doRetry();
104}
105
106void
107MemTest::sendPkt(PacketPtr pkt) {
108    if (atomic) {
109        cachePort.sendAtomic(pkt);
110        completeRequest(pkt);
111    }
112    else if (!cachePort.sendTiming(pkt)) {
113        DPRINTF(MemTest, "accessRetry setting to true\n");
114
115        //
116        // dma requests should never be retried
117        //
118        if (issueDmas) {
119            panic("Nacked DMA requests are not supported\n");
120        }
121        accessRetry = true;
122        retryPkt = pkt;
123    } else {
124        if (issueDmas) {
125            dmaOutstanding = true;
126        }
127    }
128
129}
130
131MemTest::MemTest(const Params *p)
132    : MemObject(p),
133      tickEvent(this),
134      cachePort("test", this),
135      funcPort("functional", this),
136      retryPkt(NULL),
137//      mainMem(main_mem),
138//      checkMem(check_mem),
139      size(p->memory_size),
140      percentReads(p->percent_reads),
141      percentFunctional(p->percent_functional),
142      percentUncacheable(p->percent_uncacheable),
143      issueDmas(p->issue_dmas),
144      progressInterval(p->progress_interval),
145      nextProgressMessage(p->progress_interval),
146      percentSourceUnaligned(p->percent_source_unaligned),
147      percentDestUnaligned(p->percent_dest_unaligned),
148      maxLoads(p->max_loads),
149      atomic(p->atomic)
150{
151    cachePort.snoopRangeSent = false;
152    funcPort.snoopRangeSent = true;
153
154    id = TESTER_ALLOCATOR++;
155
156    // Needs to be masked off once we know the block size.
157    traceBlockAddr = p->trace_addr;
158    baseAddr1 = 0x100000;
159    baseAddr2 = 0x400000;
160    uncacheAddr = 0x800000;
161
162    // set up counters
163    noResponseCycles = 0;
164    numReads = 0;
165    schedule(tickEvent, 0);
166
167    accessRetry = false;
168    dmaOutstanding = false;
169}
170
171Port *
172MemTest::getPort(const std::string &if_name, int idx)
173{
174    if (if_name == "functional")
175        return &funcPort;
176    else if (if_name == "test")
177        return &cachePort;
178    else
179        panic("No Such Port\n");
180}
181
182void
183MemTest::init()
184{
185    // By the time init() is called, the ports should be hooked up.
186    blockSize = cachePort.peerBlockSize();
187    blockAddrMask = blockSize - 1;
188    traceBlockAddr = blockAddr(traceBlockAddr);
189
190    // initial memory contents for both physical memory and functional
191    // memory should be 0; no need to initialize them.
192}
193
194
195void
196MemTest::completeRequest(PacketPtr pkt)
197{
198    Request *req = pkt->req;
199
200    if (issueDmas) {
201        dmaOutstanding = false;
202    }
203
204    DPRINTF(MemTest, "completing %s at address %x (blk %x)\n",
205            pkt->isWrite() ? "write" : "read",
206            req->getPaddr(), blockAddr(req->getPaddr()));
207
208    MemTestSenderState *state =
209        dynamic_cast<MemTestSenderState *>(pkt->senderState);
210
211    uint8_t *data = state->data;
212    uint8_t *pkt_data = pkt->getPtr<uint8_t>();
213
214    //Remove the address from the list of outstanding
215    std::set<unsigned>::iterator removeAddr =
216        outstandingAddrs.find(req->getPaddr());
217    assert(removeAddr != outstandingAddrs.end());
218    outstandingAddrs.erase(removeAddr);
219
220    if (pkt->isRead()) {
221        if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
222            panic("%s: read of %x (blk %x) @ cycle %d "
223                  "returns %x, expected %x\n", name(),
224                  req->getPaddr(), blockAddr(req->getPaddr()), curTick(),
225                  *pkt_data, *data);
226        }
227
228        numReads++;
229        numReadsStat++;
230
231        if (numReads == (uint64_t)nextProgressMessage) {
232            ccprintf(cerr, "%s: completed %d read accesses @%d\n",
233                     name(), numReads, curTick());
234            nextProgressMessage += progressInterval;
235        }
236
237        if (maxLoads != 0 && numReads >= maxLoads)
238            exitSimLoop("maximum number of loads reached");
239    } else {
240        assert(pkt->isWrite());
241        numWritesStat++;
242    }
243
244    noResponseCycles = 0;
245    delete state;
246    delete [] data;
247    delete pkt->req;
248    delete pkt;
249}
250
251void
252MemTest::regStats()
253{
254    using namespace Stats;
255
256    numReadsStat
257        .name(name() + ".num_reads")
258        .desc("number of read accesses completed")
259        ;
260
261    numWritesStat
262        .name(name() + ".num_writes")
263        .desc("number of write accesses completed")
264        ;
265
266    numCopiesStat
267        .name(name() + ".num_copies")
268        .desc("number of copy accesses completed")
269        ;
270}
271
272void
273MemTest::tick()
274{
275    if (!tickEvent.scheduled())
276        schedule(tickEvent, curTick() + ticks(1));
277
278    if (++noResponseCycles >= 500000) {
279        if (issueDmas) {
280            cerr << "DMA tester ";
281        }
282        cerr << name() << ": deadlocked at cycle " << curTick() << endl;
283        fatal("");
284    }
285
286    if (accessRetry || (issueDmas && dmaOutstanding)) {
287        DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n");
288        return;
289    }
290
291    //make new request
292    unsigned cmd = random() % 100;
293    unsigned offset = random() % size;
294    unsigned base = random() % 2;
295    uint64_t data = random();
296    unsigned access_size = random() % 4;
297    bool uncacheable = (random() % 100) < percentUncacheable;
298
299    unsigned dma_access_size = random() % 4;
300
301    //If we aren't doing copies, use id as offset, and do a false sharing
302    //mem tester
303    //We can eliminate the lower bits of the offset, and then use the id
304    //to offset within the blks
305    offset = blockAddr(offset);
306    offset += id;
307    access_size = 0;
308    dma_access_size = 0;
309
310    Request *req = new Request();
311    Request::Flags flags;
312    Addr paddr;
313
314    if (uncacheable) {
315        flags.set(Request::UNCACHEABLE);
316        paddr = uncacheAddr + offset;
317    } else  {
318        paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
319    }
320    bool do_functional = (random() % 100 < percentFunctional) && !uncacheable;
321
322    if (issueDmas) {
323        paddr &= ~((1 << dma_access_size) - 1);
324        req->setPhys(paddr, 1 << dma_access_size, flags);
325        req->setThreadContext(id,0);
326    } else {
327        paddr &= ~((1 << access_size) - 1);
328        req->setPhys(paddr, 1 << access_size, flags);
329        req->setThreadContext(id,0);
330    }
331    assert(req->getSize() == 1);
332
333    uint8_t *result = new uint8_t[8];
334
335    if (cmd < percentReads) {
336        // read
337
338        // For now we only allow one outstanding request per address
339        // per tester This means we assume CPU does write forwarding
340        // to reads that alias something in the cpu store buffer.
341        if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
342            delete [] result;
343            delete req;
344            return;
345        }
346
347        outstandingAddrs.insert(paddr);
348
349        // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
350        funcPort.readBlob(req->getPaddr(), result, req->getSize());
351
352        DPRINTF(MemTest,
353                "id %d initiating %sread at addr %x (blk %x) expecting %x\n",
354                id, do_functional ? "functional " : "", req->getPaddr(),
355                blockAddr(req->getPaddr()), *result);
356
357        PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
358        pkt->setSrc(0);
359        pkt->dataDynamicArray(new uint8_t[req->getSize()]);
360        MemTestSenderState *state = new MemTestSenderState(result);
361        pkt->senderState = state;
362
363        if (do_functional) {
364            cachePort.sendFunctional(pkt);
365            completeRequest(pkt);
366        } else {
367            sendPkt(pkt);
368        }
369    } else {
370        // write
371
372        // For now we only allow one outstanding request per addreess
373        // per tester.  This means we assume CPU does write forwarding
374        // to reads that alias something in the cpu store buffer.
375        if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
376            delete [] result;
377            delete req;
378            return;
379        }
380
381        outstandingAddrs.insert(paddr);
382
383        DPRINTF(MemTest, "initiating %swrite at addr %x (blk %x) value %x\n",
384                do_functional ? "functional " : "", req->getPaddr(),
385                blockAddr(req->getPaddr()), data & 0xff);
386
387        PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
388        pkt->setSrc(0);
389        uint8_t *pkt_data = new uint8_t[req->getSize()];
390        pkt->dataDynamicArray(pkt_data);
391        memcpy(pkt_data, &data, req->getSize());
392        MemTestSenderState *state = new MemTestSenderState(result);
393        pkt->senderState = state;
394
395        funcPort.writeBlob(req->getPaddr(), pkt_data, req->getSize());
396
397        if (do_functional) {
398            cachePort.sendFunctional(pkt);
399            completeRequest(pkt);
400        } else {
401            sendPkt(pkt);
402        }
403    }
404}
405
406void
407MemTest::doRetry()
408{
409    if (cachePort.sendTiming(retryPkt)) {
410        DPRINTF(MemTest, "accessRetry setting to false\n");
411        accessRetry = false;
412        retryPkt = NULL;
413    }
414}
415
416
417void
418MemTest::printAddr(Addr a)
419{
420    cachePort.printAddr(a);
421}
422
423
424MemTest *
425MemTestParams::create()
426{
427    return new MemTest(this);
428}
429