memtest.cc revision 4626
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 * Steve Reinhardt 30 */ 31 32// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded 33 34#include <iomanip> 35#include <set> 36#include <string> 37#include <vector> 38 39#include "base/misc.hh" 40#include "base/statistics.hh" 41#include "cpu/memtest/memtest.hh" 42//#include "cpu/simple_thread.hh" 43//#include "mem/cache/base_cache.hh" 44#include "mem/mem_object.hh" 45#include "mem/port.hh" 46#include "mem/packet.hh" 47//#include "mem/physical.hh" 48#include "mem/request.hh" 49#include "sim/builder.hh" 50#include "sim/sim_events.hh" 51#include "sim/stats.hh" 52 53using namespace std; 54 55int TESTER_ALLOCATOR=0; 56 57bool 58MemTest::CpuPort::recvTiming(PacketPtr pkt) 59{ 60 memtest->completeRequest(pkt); 61 return true; 62} 63 64Tick 65MemTest::CpuPort::recvAtomic(PacketPtr pkt) 66{ 67 panic("MemTest doesn't expect recvAtomic callback!"); 68 return curTick; 69} 70 71void 72MemTest::CpuPort::recvFunctional(PacketPtr pkt) 73{ 74 //Do nothing if we see one come through 75// if (curTick != 0)//Supress warning durring initialization 76// warn("Functional Writes not implemented in MemTester\n"); 77 //Need to find any response values that intersect and update 78 return; 79} 80 81void 82MemTest::CpuPort::recvStatusChange(Status status) 83{ 84 if (status == RangeChange) { 85 if (!snoopRangeSent) { 86 snoopRangeSent = true; 87 sendStatusChange(Port::RangeChange); 88 } 89 return; 90 } 91 92 panic("MemTest doesn't expect recvStatusChange callback!"); 93} 94 95void 96MemTest::CpuPort::recvRetry() 97{ 98 memtest->doRetry(); 99} 100 101void 102MemTest::sendPkt(PacketPtr pkt) { 103 if (atomic) { 104 cachePort.sendAtomic(pkt); 105 completeRequest(pkt); 106 } 107 else if (!cachePort.sendTiming(pkt)) { 108 accessRetry = true; 109 retryPkt = pkt; 110 } 111 112} 113 114MemTest::MemTest(const string &name, 115// MemInterface *_cache_interface, 116// PhysicalMemory *main_mem, 117// PhysicalMemory *check_mem, 118 unsigned _memorySize, 119 unsigned _percentReads, 120 unsigned _percentFunctional, 121 unsigned _percentUncacheable, 122 unsigned _progressInterval, 123 unsigned _percentSourceUnaligned, 124 unsigned _percentDestUnaligned, 125 Addr _traceAddr, 126 Counter _max_loads, 127 bool _atomic) 128 : MemObject(name), 129 tickEvent(this), 130 cachePort("test", this), 131 funcPort("functional", this), 132 retryPkt(NULL), 133// mainMem(main_mem), 134// checkMem(check_mem), 135 size(_memorySize), 136 percentReads(_percentReads), 137 percentFunctional(_percentFunctional), 138 percentUncacheable(_percentUncacheable), 139 progressInterval(_progressInterval), 140 nextProgressMessage(_progressInterval), 141 percentSourceUnaligned(_percentSourceUnaligned), 142 percentDestUnaligned(percentDestUnaligned), 143 maxLoads(_max_loads), 144 atomic(_atomic) 145{ 146 vector<string> cmd; 147 cmd.push_back("/bin/ls"); 148 vector<string> null_vec; 149 // thread = new SimpleThread(NULL, 0, NULL, 0, mainMem); 150 curTick = 0; 151 152 cachePort.snoopRangeSent = false; 153 funcPort.snoopRangeSent = true; 154 155 // Needs to be masked off once we know the block size. 156 traceBlockAddr = _traceAddr; 157 baseAddr1 = 0x100000; 158 baseAddr2 = 0x400000; 159 uncacheAddr = 0x800000; 160 161 // set up counters 162 noResponseCycles = 0; 163 numReads = 0; 164 tickEvent.schedule(0); 165 166 id = TESTER_ALLOCATOR++; 167 168 accessRetry = false; 169} 170 171Port * 172MemTest::getPort(const std::string &if_name, int idx) 173{ 174 if (if_name == "functional") 175 return &funcPort; 176 else if (if_name == "test") 177 return &cachePort; 178 else 179 panic("No Such Port\n"); 180} 181 182void 183MemTest::init() 184{ 185 // By the time init() is called, the ports should be hooked up. 186 blockSize = cachePort.peerBlockSize(); 187 blockAddrMask = blockSize - 1; 188 traceBlockAddr = blockAddr(traceBlockAddr); 189 190 // initial memory contents for both physical memory and functional 191 // memory should be 0; no need to initialize them. 192} 193 194static void 195printData(ostream &os, uint8_t *data, int nbytes) 196{ 197 os << hex << setfill('0'); 198 // assume little-endian: print bytes from highest address to lowest 199 for (uint8_t *dp = data + nbytes - 1; dp >= data; --dp) { 200 os << setw(2) << (unsigned)*dp; 201 } 202 os << dec; 203} 204 205void 206MemTest::completeRequest(PacketPtr pkt) 207{ 208 MemTestSenderState *state = 209 dynamic_cast<MemTestSenderState *>(pkt->senderState); 210 211 uint8_t *data = state->data; 212 uint8_t *pkt_data = pkt->getPtr<uint8_t>(); 213 Request *req = pkt->req; 214 215 //Remove the address from the list of outstanding 216 std::set<unsigned>::iterator removeAddr = outstandingAddrs.find(req->getPaddr()); 217 assert(removeAddr != outstandingAddrs.end()); 218 outstandingAddrs.erase(removeAddr); 219 220 switch (pkt->cmd.toInt()) { 221 case MemCmd::ReadResp: 222 223 if (memcmp(pkt_data, data, pkt->getSize()) != 0) { 224 panic("%s: read of %x (blk %x) @ cycle %d " 225 "returns %x, expected %x\n", name(), 226 req->getPaddr(), blockAddr(req->getPaddr()), curTick, 227 *pkt_data, *data); 228 } 229 230 numReads++; 231 numReadsStat++; 232 233 if (numReads == nextProgressMessage) { 234 ccprintf(cerr, "%s: completed %d read accesses @%d\n", 235 name(), numReads, curTick); 236 nextProgressMessage += progressInterval; 237 } 238 239 if (numReads >= maxLoads) 240 exitSimLoop("Maximum number of loads reached!"); 241 break; 242 243 case MemCmd::WriteResp: 244 numWritesStat++; 245 break; 246/* 247 case Copy: 248 //Also remove dest from outstanding list 249 removeAddr = outstandingAddrs.find(req->dest); 250 assert(removeAddr != outstandingAddrs.end()); 251 outstandingAddrs.erase(removeAddr); 252 numCopiesStat++; 253 break; 254*/ 255 default: 256 panic("invalid command %s (%d)", pkt->cmdString(), pkt->cmd.toInt()); 257 } 258 259 if (blockAddr(req->getPaddr()) == traceBlockAddr) { 260 cerr << name() << ": completed " 261 << (pkt->isWrite() ? "write" : "read") 262 << " access of " 263 << dec << pkt->getSize() << " bytes at address 0x" 264 << hex << req->getPaddr() 265 << " (0x" << hex << blockAddr(req->getPaddr()) << ")" 266 << ", value = 0x"; 267 printData(cerr, pkt_data, pkt->getSize()); 268 cerr << " @ cycle " << dec << curTick; 269 270 cerr << endl; 271 } 272 273 noResponseCycles = 0; 274 delete state; 275 delete [] data; 276 delete pkt->req; 277 delete pkt; 278} 279 280void 281MemTest::regStats() 282{ 283 using namespace Stats; 284 285 numReadsStat 286 .name(name() + ".num_reads") 287 .desc("number of read accesses completed") 288 ; 289 290 numWritesStat 291 .name(name() + ".num_writes") 292 .desc("number of write accesses completed") 293 ; 294 295 numCopiesStat 296 .name(name() + ".num_copies") 297 .desc("number of copy accesses completed") 298 ; 299} 300 301void 302MemTest::tick() 303{ 304 if (!tickEvent.scheduled()) 305 tickEvent.schedule(curTick + cycles(1)); 306 307 if (++noResponseCycles >= 500000) { 308 cerr << name() << ": deadlocked at cycle " << curTick << endl; 309 fatal(""); 310 } 311 312 if (accessRetry) { 313 return; 314 } 315 316 //make new request 317 unsigned cmd = random() % 100; 318 unsigned offset = random() % size; 319 unsigned base = random() % 2; 320 uint64_t data = random(); 321 unsigned access_size = random() % 4; 322 unsigned cacheable = random() % 100; 323 324 //If we aren't doing copies, use id as offset, and do a false sharing 325 //mem tester 326 //We can eliminate the lower bits of the offset, and then use the id 327 //to offset within the blks 328 offset &= ~63; //Not the low order bits 329 offset += id; 330 access_size = 0; 331 332 Request *req = new Request(); 333 uint32_t flags = 0; 334 Addr paddr; 335 336 if (cacheable < percentUncacheable) { 337 flags |= UNCACHEABLE; 338 paddr = uncacheAddr + offset; 339 } else { 340 paddr = ((base) ? baseAddr1 : baseAddr2) + offset; 341 } 342 bool probe = (random() % 100 < percentFunctional) && !(flags & UNCACHEABLE); 343 //bool probe = false; 344 345 paddr &= ~((1 << access_size) - 1); 346 req->setPhys(paddr, 1 << access_size, flags); 347 req->setThreadContext(id,0); 348 349 uint8_t *result = new uint8_t[8]; 350 351 if (cmd < percentReads) { 352 // read 353 354 //For now we only allow one outstanding request per addreess per tester 355 //This means we assume CPU does write forwarding to reads that alias something 356 //in the cpu store buffer. 357 if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { 358 delete [] result; 359 delete req; 360 return; 361 } 362 else outstandingAddrs.insert(paddr); 363 364 // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin 365 funcPort.readBlob(req->getPaddr(), result, req->getSize()); 366 367 if (blockAddr(paddr) == traceBlockAddr) { 368 cerr << name() 369 << ": initiating read " 370 << ((probe) ? "probe of " : "access of ") 371 << dec << req->getSize() << " bytes from addr 0x" 372 << hex << paddr 373 << " (0x" << hex << blockAddr(paddr) << ")" 374 << " at cycle " 375 << dec << curTick << endl; 376 } 377 378 PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 379 pkt->dataDynamicArray(new uint8_t[req->getSize()]); 380 MemTestSenderState *state = new MemTestSenderState(result); 381 pkt->senderState = state; 382 383 if (probe) { 384 cachePort.sendFunctional(pkt); 385 pkt->makeAtomicResponse(); 386 completeRequest(pkt); 387 } else { 388// req->completionEvent = new MemCompleteEvent(req, result, this); 389 sendPkt(pkt); 390 } 391 } else { 392 // write 393 394 //For now we only allow one outstanding request per addreess per tester 395 //This means we assume CPU does write forwarding to reads that alias something 396 //in the cpu store buffer. 397 if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { 398 delete [] result; 399 delete req; 400 return; 401 } 402 403 else outstandingAddrs.insert(paddr); 404 405/* 406 if (blockAddr(req->getPaddr()) == traceBlockAddr) { 407 cerr << name() << ": initiating write " 408 << ((probe)?"probe of ":"access of ") 409 << dec << req->getSize() << " bytes (value = 0x"; 410 printData(cerr, data_pkt->getPtr(), req->getSize()); 411 cerr << ") to addr 0x" 412 << hex << req->getPaddr() 413 << " (0x" << hex << blockAddr(req->getPaddr()) << ")" 414 << " at cycle " 415 << dec << curTick << endl; 416 } 417*/ 418 PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast); 419 uint8_t *pkt_data = new uint8_t[req->getSize()]; 420 pkt->dataDynamicArray(pkt_data); 421 memcpy(pkt_data, &data, req->getSize()); 422 MemTestSenderState *state = new MemTestSenderState(result); 423 pkt->senderState = state; 424 425 funcPort.writeBlob(req->getPaddr(), pkt_data, req->getSize()); 426 427 if (probe) { 428 cachePort.sendFunctional(pkt); 429 pkt->makeAtomicResponse(); 430 completeRequest(pkt); 431 } else { 432// req->completionEvent = new MemCompleteEvent(req, NULL, this); 433 sendPkt(pkt); 434 } 435 } 436/* else { 437 // copy 438 unsigned source_align = random() % 100; 439 unsigned dest_align = random() % 100; 440 unsigned offset2 = random() % size; 441 442 Addr source = ((base) ? baseAddr1 : baseAddr2) + offset; 443 Addr dest = ((base) ? baseAddr2 : baseAddr1) + offset2; 444 if (outstandingAddrs.find(source) != outstandingAddrs.end()) return; 445 else outstandingAddrs.insert(source); 446 if (outstandingAddrs.find(dest) != outstandingAddrs.end()) return; 447 else outstandingAddrs.insert(dest); 448 449 if (source_align >= percentSourceUnaligned) { 450 source = blockAddr(source); 451 } 452 if (dest_align >= percentDestUnaligned) { 453 dest = blockAddr(dest); 454 } 455 req->cmd = Copy; 456 req->flags &= ~UNCACHEABLE; 457 req->paddr = source; 458 req->dest = dest; 459 delete [] req->data; 460 req->data = new uint8_t[blockSize]; 461 req->size = blockSize; 462 if (source == traceBlockAddr || dest == traceBlockAddr) { 463 cerr << name() 464 << ": initiating copy of " 465 << dec << req->size << " bytes from addr 0x" 466 << hex << source 467 << " (0x" << hex << blockAddr(source) << ")" 468 << " to addr 0x" 469 << hex << dest 470 << " (0x" << hex << blockAddr(dest) << ")" 471 << " at cycle " 472 << dec << curTick << endl; 473 }* 474 cacheInterface->access(req); 475 uint8_t result[blockSize]; 476 checkMem->access(Read, source, &result, blockSize); 477 checkMem->access(Write, dest, &result, blockSize); 478 } 479*/ 480} 481 482void 483MemTest::doRetry() 484{ 485 if (cachePort.sendTiming(retryPkt)) { 486 accessRetry = false; 487 retryPkt = NULL; 488 } 489} 490 491BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest) 492 493// SimObjectParam<BaseCache *> cache; 494// SimObjectParam<PhysicalMemory *> main_mem; 495// SimObjectParam<PhysicalMemory *> check_mem; 496 Param<unsigned> memory_size; 497 Param<unsigned> percent_reads; 498 Param<unsigned> percent_functional; 499 Param<unsigned> percent_uncacheable; 500 Param<unsigned> progress_interval; 501 Param<unsigned> percent_source_unaligned; 502 Param<unsigned> percent_dest_unaligned; 503 Param<Addr> trace_addr; 504 Param<Counter> max_loads; 505 Param<bool> atomic; 506 507END_DECLARE_SIM_OBJECT_PARAMS(MemTest) 508 509 510BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest) 511 512// INIT_PARAM(cache, "L1 cache"), 513// INIT_PARAM(main_mem, "hierarchical memory"), 514// INIT_PARAM(check_mem, "check memory"), 515 INIT_PARAM(memory_size, "memory size"), 516 INIT_PARAM(percent_reads, "target read percentage"), 517 INIT_PARAM(percent_functional, "percentage of access that are functional"), 518 INIT_PARAM(percent_uncacheable, "target uncacheable percentage"), 519 INIT_PARAM(progress_interval, "progress report interval (in accesses)"), 520 INIT_PARAM(percent_source_unaligned, 521 "percent of copy source address that are unaligned"), 522 INIT_PARAM(percent_dest_unaligned, 523 "percent of copy dest address that are unaligned"), 524 INIT_PARAM(trace_addr, "address to trace"), 525 INIT_PARAM(max_loads, "terminate when we have reached this load count"), 526 INIT_PARAM(atomic, "Is the tester testing atomic mode (or timing)") 527 528END_INIT_SIM_OBJECT_PARAMS(MemTest) 529 530 531CREATE_SIM_OBJECT(MemTest) 532{ 533 return new MemTest(getInstanceName(), /*cache->getInterface(),*/ /*main_mem,*/ 534 /*check_mem,*/ memory_size, percent_reads, percent_functional, 535 percent_uncacheable, progress_interval, 536 percent_source_unaligned, percent_dest_unaligned, 537 trace_addr, max_loads, atomic); 538} 539 540REGISTER_SIM_OBJECT("MemTest", MemTest) 541