memtest.cc revision 10376:28c63d075e0c
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 * Steve Reinhardt 30 */ 31 32// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded 33 34#include <iomanip> 35#include <set> 36#include <string> 37#include <vector> 38 39#include "base/misc.hh" 40#include "base/random.hh" 41#include "base/statistics.hh" 42#include "cpu/testers/memtest/memtest.hh" 43#include "debug/MemTest.hh" 44#include "mem/mem_object.hh" 45#include "mem/packet.hh" 46#include "mem/port.hh" 47#include "mem/request.hh" 48#include "sim/sim_events.hh" 49#include "sim/stats.hh" 50#include "sim/system.hh" 51 52using namespace std; 53 54int TESTER_ALLOCATOR=0; 55 56bool 57MemTest::CpuPort::recvTimingResp(PacketPtr pkt) 58{ 59 memtest->completeRequest(pkt); 60 return true; 61} 62 63void 64MemTest::CpuPort::recvRetry() 65{ 66 memtest->doRetry(); 67} 68 69void 70MemTest::sendPkt(PacketPtr pkt) { 71 if (atomic) { 72 cachePort.sendAtomic(pkt); 73 completeRequest(pkt); 74 } 75 else if (!cachePort.sendTimingReq(pkt)) { 76 DPRINTF(MemTest, "accessRetry setting to true\n"); 77 78 // 79 // dma requests should never be retried 80 // 81 if (issueDmas) { 82 panic("Nacked DMA requests are not supported\n"); 83 } 84 accessRetry = true; 85 retryPkt = pkt; 86 } else { 87 if (issueDmas) { 88 dmaOutstanding = true; 89 } 90 } 91 92} 93 94MemTest::MemTest(const Params *p) 95 : MemObject(p), 96 tickEvent(this), 97 cachePort("test", this), 98 funcPort("functional", this), 99 funcProxy(funcPort, p->sys->cacheLineSize()), 100 retryPkt(NULL), 101// mainMem(main_mem), 102// checkMem(check_mem), 103 size(p->memory_size), 104 percentReads(p->percent_reads), 105 percentFunctional(p->percent_functional), 106 percentUncacheable(p->percent_uncacheable), 107 issueDmas(p->issue_dmas), 108 masterId(p->sys->getMasterId(name())), 109 blockSize(p->sys->cacheLineSize()), 110 progressInterval(p->progress_interval), 111 nextProgressMessage(p->progress_interval), 112 percentSourceUnaligned(p->percent_source_unaligned), 113 percentDestUnaligned(p->percent_dest_unaligned), 114 maxLoads(p->max_loads), 115 atomic(p->atomic), 116 suppress_func_warnings(p->suppress_func_warnings) 117{ 118 id = TESTER_ALLOCATOR++; 119 120 // Needs to be masked off once we know the block size. 121 traceBlockAddr = p->trace_addr; 122 baseAddr1 = 0x100000; 123 baseAddr2 = 0x400000; 124 uncacheAddr = 0x800000; 125 126 blockAddrMask = blockSize - 1; 127 traceBlockAddr = blockAddr(traceBlockAddr); 128 129 // set up counters 130 noResponseCycles = 0; 131 numReads = 0; 132 numWrites = 0; 133 schedule(tickEvent, 0); 134 135 accessRetry = false; 136 dmaOutstanding = false; 137} 138 139BaseMasterPort & 140MemTest::getMasterPort(const std::string &if_name, PortID idx) 141{ 142 if (if_name == "functional") 143 return funcPort; 144 else if (if_name == "test") 145 return cachePort; 146 else 147 return MemObject::getMasterPort(if_name, idx); 148} 149 150void 151MemTest::init() 152{ 153 // initial memory contents for both physical memory and functional 154 // memory should be 0; no need to initialize them. 155} 156 157 158void 159MemTest::completeRequest(PacketPtr pkt) 160{ 161 Request *req = pkt->req; 162 163 if (issueDmas) { 164 dmaOutstanding = false; 165 } 166 167 DPRINTF(MemTest, "completing %s at address %x (blk %x) %s\n", 168 pkt->isWrite() ? "write" : "read", 169 req->getPaddr(), blockAddr(req->getPaddr()), 170 pkt->isError() ? "error" : "success"); 171 172 MemTestSenderState *state = 173 safe_cast<MemTestSenderState *>(pkt->senderState); 174 175 uint8_t *data = state->data; 176 uint8_t *pkt_data = pkt->getPtr<uint8_t>(); 177 178 //Remove the address from the list of outstanding 179 std::set<unsigned>::iterator removeAddr = 180 outstandingAddrs.find(req->getPaddr()); 181 assert(removeAddr != outstandingAddrs.end()); 182 outstandingAddrs.erase(removeAddr); 183 184 if (pkt->isError()) { 185 if (!suppress_func_warnings) { 186 warn("Functional %s access failed at %#x\n", 187 pkt->isWrite() ? "write" : "read", req->getPaddr()); 188 } 189 } else { 190 if (pkt->isRead()) { 191 if (memcmp(pkt_data, data, pkt->getSize()) != 0) { 192 panic("%s: read of %x (blk %x) @ cycle %d " 193 "returns %x, expected %x\n", name(), 194 req->getPaddr(), blockAddr(req->getPaddr()), curTick(), 195 *pkt_data, *data); 196 } 197 198 numReads++; 199 numReadsStat++; 200 201 if (numReads == (uint64_t)nextProgressMessage) { 202 ccprintf(cerr, "%s: completed %d read, %d write accesses @%d\n", 203 name(), numReads, numWrites, curTick()); 204 nextProgressMessage += progressInterval; 205 } 206 207 if (maxLoads != 0 && numReads >= maxLoads) 208 exitSimLoop("maximum number of loads reached"); 209 } else { 210 assert(pkt->isWrite()); 211 funcProxy.writeBlob(req->getPaddr(), pkt_data, req->getSize()); 212 numWrites++; 213 numWritesStat++; 214 } 215 } 216 217 noResponseCycles = 0; 218 delete state; 219 delete [] data; 220 delete pkt->req; 221 delete pkt; 222} 223 224void 225MemTest::regStats() 226{ 227 using namespace Stats; 228 229 numReadsStat 230 .name(name() + ".num_reads") 231 .desc("number of read accesses completed") 232 ; 233 234 numWritesStat 235 .name(name() + ".num_writes") 236 .desc("number of write accesses completed") 237 ; 238 239 numCopiesStat 240 .name(name() + ".num_copies") 241 .desc("number of copy accesses completed") 242 ; 243} 244 245void 246MemTest::tick() 247{ 248 if (!tickEvent.scheduled()) 249 schedule(tickEvent, clockEdge(Cycles(1))); 250 251 if (++noResponseCycles >= 500000) { 252 if (issueDmas) { 253 cerr << "DMA tester "; 254 } 255 cerr << name() << ": deadlocked at cycle " << curTick() << endl; 256 fatal(""); 257 } 258 259 if (accessRetry || (issueDmas && dmaOutstanding)) { 260 DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n"); 261 return; 262 } 263 264 //make new request 265 unsigned cmd = random_mt.random(0, 100); 266 unsigned offset = random_mt.random<unsigned>(0, size - 1); 267 unsigned base = random_mt.random(0, 1); 268 uint64_t data = random_mt.random<uint64_t>(); 269 unsigned access_size = random_mt.random(0, 3); 270 bool uncacheable = random_mt.random(0, 100) < percentUncacheable; 271 272 unsigned dma_access_size = random_mt.random(0, 3); 273 274 //If we aren't doing copies, use id as offset, and do a false sharing 275 //mem tester 276 //We can eliminate the lower bits of the offset, and then use the id 277 //to offset within the blks 278 offset = blockAddr(offset); 279 offset += id; 280 access_size = 0; 281 dma_access_size = 0; 282 283 Request::Flags flags; 284 Addr paddr; 285 286 if (uncacheable) { 287 flags.set(Request::UNCACHEABLE); 288 paddr = uncacheAddr + offset; 289 } else { 290 paddr = ((base) ? baseAddr1 : baseAddr2) + offset; 291 } 292 293 // For now we only allow one outstanding request per address 294 // per tester This means we assume CPU does write forwarding 295 // to reads that alias something in the cpu store buffer. 296 if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { 297 return; 298 } 299 300 bool do_functional = (random_mt.random(0, 100) < percentFunctional) && 301 !uncacheable; 302 Request *req = new Request(); 303 uint8_t *result = new uint8_t[8]; 304 305 if (issueDmas) { 306 paddr &= ~((1 << dma_access_size) - 1); 307 req->setPhys(paddr, 1 << dma_access_size, flags, masterId); 308 req->setThreadContext(id,0); 309 } else { 310 paddr &= ~((1 << access_size) - 1); 311 req->setPhys(paddr, 1 << access_size, flags, masterId); 312 req->setThreadContext(id,0); 313 } 314 assert(req->getSize() == 1); 315 316 if (cmd < percentReads) { 317 // read 318 outstandingAddrs.insert(paddr); 319 320 // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin 321 funcProxy.readBlob(req->getPaddr(), result, req->getSize()); 322 323 DPRINTF(MemTest, 324 "id %d initiating %sread at addr %x (blk %x) expecting %x\n", 325 id, do_functional ? "functional " : "", req->getPaddr(), 326 blockAddr(req->getPaddr()), *result); 327 328 PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 329 pkt->dataDynamicArray(new uint8_t[req->getSize()]); 330 MemTestSenderState *state = new MemTestSenderState(result); 331 pkt->senderState = state; 332 333 if (do_functional) { 334 assert(pkt->needsResponse()); 335 pkt->setSuppressFuncError(); 336 cachePort.sendFunctional(pkt); 337 completeRequest(pkt); 338 } else { 339 sendPkt(pkt); 340 } 341 } else { 342 // write 343 outstandingAddrs.insert(paddr); 344 345 DPRINTF(MemTest, "initiating %swrite at addr %x (blk %x) value %x\n", 346 do_functional ? "functional " : "", req->getPaddr(), 347 blockAddr(req->getPaddr()), data & 0xff); 348 349 PacketPtr pkt = new Packet(req, MemCmd::WriteReq); 350 uint8_t *pkt_data = new uint8_t[req->getSize()]; 351 pkt->dataDynamicArray(pkt_data); 352 memcpy(pkt_data, &data, req->getSize()); 353 MemTestSenderState *state = new MemTestSenderState(result); 354 pkt->senderState = state; 355 356 if (do_functional) { 357 pkt->setSuppressFuncError(); 358 cachePort.sendFunctional(pkt); 359 completeRequest(pkt); 360 } else { 361 sendPkt(pkt); 362 } 363 } 364} 365 366void 367MemTest::doRetry() 368{ 369 if (cachePort.sendTimingReq(retryPkt)) { 370 DPRINTF(MemTest, "accessRetry setting to false\n"); 371 accessRetry = false; 372 retryPkt = NULL; 373 } 374} 375 376 377void 378MemTest::printAddr(Addr a) 379{ 380 cachePort.printAddr(a); 381} 382 383 384MemTest * 385MemTestParams::create() 386{ 387 return new MemTest(this); 388} 389