memtest.cc revision 9294
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Erik Hallnor 292665SN/A * Steve Reinhardt 302SN/A */ 312SN/A 322SN/A// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded 332SN/A 341298SN/A#include <iomanip> 351298SN/A#include <set> 361259SN/A#include <string> 372SN/A#include <vector> 382SN/A 39146SN/A#include "base/misc.hh" 40146SN/A#include "base/statistics.hh" 417632SBrad.Beckmann@amd.com#include "cpu/testers/memtest/memtest.hh" 428232Snate@binkert.org#include "debug/MemTest.hh" 433348SN/A#include "mem/mem_object.hh" 448229Snate@binkert.org#include "mem/packet.hh" 453348SN/A#include "mem/port.hh" 463348SN/A#include "mem/request.hh" 4756SN/A#include "sim/sim_events.hh" 48695SN/A#include "sim/stats.hh" 498832SAli.Saidi@ARM.com#include "sim/system.hh" 502SN/A 512SN/Ausing namespace std; 522SN/A 531298SN/Aint TESTER_ALLOCATOR=0; 541298SN/A 553187SN/Abool 568975Sandreas.hansson@arm.comMemTest::CpuPort::recvTimingResp(PacketPtr pkt) 573187SN/A{ 588948Sandreas.hansson@arm.com memtest->completeRequest(pkt); 593187SN/A return true; 603187SN/A} 613187SN/A 623187SN/Avoid 633187SN/AMemTest::CpuPort::recvRetry() 643187SN/A{ 653187SN/A memtest->doRetry(); 663187SN/A} 673187SN/A 683262SN/Avoid 693349SN/AMemTest::sendPkt(PacketPtr pkt) { 703262SN/A if (atomic) { 713262SN/A cachePort.sendAtomic(pkt); 723262SN/A completeRequest(pkt); 733262SN/A } 748975Sandreas.hansson@arm.com else if (!cachePort.sendTimingReq(pkt)) { 757544SN/A DPRINTF(MemTest, "accessRetry setting to true\n"); 767544SN/A 777544SN/A // 787544SN/A // dma requests should never be retried 797544SN/A // 807544SN/A if (issueDmas) { 817544SN/A panic("Nacked DMA requests are not supported\n"); 827544SN/A } 833262SN/A accessRetry = true; 843262SN/A retryPkt = pkt; 857544SN/A } else { 867544SN/A if (issueDmas) { 877544SN/A dmaOutstanding = true; 887544SN/A } 893262SN/A } 903262SN/A 913262SN/A} 923262SN/A 935034SN/AMemTest::MemTest(const Params *p) 945034SN/A : MemObject(p), 952SN/A tickEvent(this), 963187SN/A cachePort("test", this), 973187SN/A funcPort("functional", this), 988853Sandreas.hansson@arm.com funcProxy(funcPort), 993187SN/A retryPkt(NULL), 1003187SN/A// mainMem(main_mem), 1013187SN/A// checkMem(check_mem), 1025034SN/A size(p->memory_size), 1035034SN/A percentReads(p->percent_reads), 1045034SN/A percentFunctional(p->percent_functional), 1055034SN/A percentUncacheable(p->percent_uncacheable), 1067544SN/A issueDmas(p->issue_dmas), 1078832SAli.Saidi@ARM.com masterId(p->sys->getMasterId(name())), 1085034SN/A progressInterval(p->progress_interval), 1095034SN/A nextProgressMessage(p->progress_interval), 1105034SN/A percentSourceUnaligned(p->percent_source_unaligned), 1115034SN/A percentDestUnaligned(p->percent_dest_unaligned), 1125034SN/A maxLoads(p->max_loads), 1138436SBrad.Beckmann@amd.com atomic(p->atomic), 1148436SBrad.Beckmann@amd.com suppress_func_warnings(p->suppress_func_warnings) 1152SN/A{ 1167544SN/A id = TESTER_ALLOCATOR++; 1177544SN/A 1183187SN/A // Needs to be masked off once we know the block size. 1195034SN/A traceBlockAddr = p->trace_addr; 1202SN/A baseAddr1 = 0x100000; 1212SN/A baseAddr2 = 0x400000; 1222SN/A uncacheAddr = 0x800000; 1232SN/A 1242SN/A // set up counters 1252SN/A noResponseCycles = 0; 1262SN/A numReads = 0; 1278436SBrad.Beckmann@amd.com numWrites = 0; 1285606SN/A schedule(tickEvent, 0); 1291298SN/A 1303187SN/A accessRetry = false; 1317544SN/A dmaOutstanding = false; 1323187SN/A} 1333187SN/A 1349294Sandreas.hansson@arm.comBaseMasterPort & 1359294Sandreas.hansson@arm.comMemTest::getMasterPort(const std::string &if_name, PortID idx) 1363187SN/A{ 1373187SN/A if (if_name == "functional") 1388922Swilliam.wang@arm.com return funcPort; 1393187SN/A else if (if_name == "test") 1408922Swilliam.wang@arm.com return cachePort; 1413187SN/A else 1428922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1433187SN/A} 1443187SN/A 1453187SN/Avoid 1463187SN/AMemTest::init() 1473187SN/A{ 1483187SN/A // By the time init() is called, the ports should be hooked up. 1493187SN/A blockSize = cachePort.peerBlockSize(); 1503187SN/A blockAddrMask = blockSize - 1; 1513187SN/A traceBlockAddr = blockAddr(traceBlockAddr); 1523187SN/A 1534579SN/A // initial memory contents for both physical memory and functional 1544579SN/A // memory should be 0; no need to initialize them. 1552SN/A} 1562SN/A 1572SN/A 1582SN/Avoid 1593349SN/AMemTest::completeRequest(PacketPtr pkt) 1602SN/A{ 1614628SN/A Request *req = pkt->req; 1624628SN/A 1637544SN/A if (issueDmas) { 1647544SN/A dmaOutstanding = false; 1657544SN/A } 1667544SN/A 1678436SBrad.Beckmann@amd.com DPRINTF(MemTest, "completing %s at address %x (blk %x) %s\n", 1684628SN/A pkt->isWrite() ? "write" : "read", 1698436SBrad.Beckmann@amd.com req->getPaddr(), blockAddr(req->getPaddr()), 1708436SBrad.Beckmann@amd.com pkt->isError() ? "error" : "success"); 1714628SN/A 1723187SN/A MemTestSenderState *state = 1733187SN/A dynamic_cast<MemTestSenderState *>(pkt->senderState); 1743187SN/A 1753187SN/A uint8_t *data = state->data; 1763187SN/A uint8_t *pkt_data = pkt->getPtr<uint8_t>(); 1773187SN/A 1781298SN/A //Remove the address from the list of outstanding 1794628SN/A std::set<unsigned>::iterator removeAddr = 1804628SN/A outstandingAddrs.find(req->getPaddr()); 1811298SN/A assert(removeAddr != outstandingAddrs.end()); 1821298SN/A outstandingAddrs.erase(removeAddr); 1831298SN/A 1848436SBrad.Beckmann@amd.com if (pkt->isError()) { 1858436SBrad.Beckmann@amd.com if (!suppress_func_warnings) { 1868436SBrad.Beckmann@amd.com warn("Functional Access failed for %x at %x\n", 1878436SBrad.Beckmann@amd.com pkt->isWrite() ? "write" : "read", req->getPaddr()); 1882SN/A } 1898436SBrad.Beckmann@amd.com } else { 1908436SBrad.Beckmann@amd.com if (pkt->isRead()) { 1918436SBrad.Beckmann@amd.com if (memcmp(pkt_data, data, pkt->getSize()) != 0) { 1928436SBrad.Beckmann@amd.com panic("%s: read of %x (blk %x) @ cycle %d " 1938436SBrad.Beckmann@amd.com "returns %x, expected %x\n", name(), 1948436SBrad.Beckmann@amd.com req->getPaddr(), blockAddr(req->getPaddr()), curTick(), 1958436SBrad.Beckmann@amd.com *pkt_data, *data); 1968436SBrad.Beckmann@amd.com } 1972SN/A 1988436SBrad.Beckmann@amd.com numReads++; 1998436SBrad.Beckmann@amd.com numReadsStat++; 2002SN/A 2018436SBrad.Beckmann@amd.com if (numReads == (uint64_t)nextProgressMessage) { 2028436SBrad.Beckmann@amd.com ccprintf(cerr, "%s: completed %d read, %d write accesses @%d\n", 2038436SBrad.Beckmann@amd.com name(), numReads, numWrites, curTick()); 2048436SBrad.Beckmann@amd.com nextProgressMessage += progressInterval; 2058436SBrad.Beckmann@amd.com } 2068436SBrad.Beckmann@amd.com 2078436SBrad.Beckmann@amd.com if (maxLoads != 0 && numReads >= maxLoads) 2088436SBrad.Beckmann@amd.com exitSimLoop("maximum number of loads reached"); 2098436SBrad.Beckmann@amd.com } else { 2108436SBrad.Beckmann@amd.com assert(pkt->isWrite()); 2118853Sandreas.hansson@arm.com funcProxy.writeBlob(req->getPaddr(), pkt_data, req->getSize()); 2128436SBrad.Beckmann@amd.com numWrites++; 2138436SBrad.Beckmann@amd.com numWritesStat++; 2142SN/A } 2152SN/A } 2162SN/A 2172SN/A noResponseCycles = 0; 2183187SN/A delete state; 2192SN/A delete [] data; 2203187SN/A delete pkt->req; 2213187SN/A delete pkt; 2222SN/A} 2232SN/A 2242SN/Avoid 2252SN/AMemTest::regStats() 2262SN/A{ 227729SN/A using namespace Stats; 2282SN/A 229695SN/A numReadsStat 2302SN/A .name(name() + ".num_reads") 2312SN/A .desc("number of read accesses completed") 2322SN/A ; 2332SN/A 234695SN/A numWritesStat 2352SN/A .name(name() + ".num_writes") 2362SN/A .desc("number of write accesses completed") 2372SN/A ; 2382SN/A 239695SN/A numCopiesStat 2402SN/A .name(name() + ".num_copies") 2412SN/A .desc("number of copy accesses completed") 2422SN/A ; 2432SN/A} 2442SN/A 2452SN/Avoid 2462SN/AMemTest::tick() 2472SN/A{ 2482SN/A if (!tickEvent.scheduled()) 2499180Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(Cycles(1))); 2502SN/A 2511298SN/A if (++noResponseCycles >= 500000) { 2527544SN/A if (issueDmas) { 2537544SN/A cerr << "DMA tester "; 2547544SN/A } 2557823Ssteve.reinhardt@amd.com cerr << name() << ": deadlocked at cycle " << curTick() << endl; 2562SN/A fatal(""); 2572SN/A } 2582SN/A 2597544SN/A if (accessRetry || (issueDmas && dmaOutstanding)) { 2607544SN/A DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n"); 2612SN/A return; 2622SN/A } 2632SN/A 2642SN/A //make new request 2651899SN/A unsigned cmd = random() % 100; 2661899SN/A unsigned offset = random() % size; 2672SN/A unsigned base = random() % 2; 2682SN/A uint64_t data = random(); 2692SN/A unsigned access_size = random() % 4; 2705736SN/A bool uncacheable = (random() % 100) < percentUncacheable; 2712SN/A 2727544SN/A unsigned dma_access_size = random() % 4; 2737544SN/A 2741298SN/A //If we aren't doing copies, use id as offset, and do a false sharing 2751298SN/A //mem tester 2763187SN/A //We can eliminate the lower bits of the offset, and then use the id 2773187SN/A //to offset within the blks 2784628SN/A offset = blockAddr(offset); 2793187SN/A offset += id; 2803187SN/A access_size = 0; 2817544SN/A dma_access_size = 0; 2821298SN/A 2833187SN/A Request *req = new Request(); 2845736SN/A Request::Flags flags; 2853187SN/A Addr paddr; 2862SN/A 2875736SN/A if (uncacheable) { 2885736SN/A flags.set(Request::UNCACHEABLE); 2893187SN/A paddr = uncacheAddr + offset; 2907544SN/A } else { 2913187SN/A paddr = ((base) ? baseAddr1 : baseAddr2) + offset; 2922SN/A } 2937657Ssteve.reinhardt@amd.com bool do_functional = (random() % 100 < percentFunctional) && !uncacheable; 2942SN/A 2957544SN/A if (issueDmas) { 2967544SN/A paddr &= ~((1 << dma_access_size) - 1); 2978832SAli.Saidi@ARM.com req->setPhys(paddr, 1 << dma_access_size, flags, masterId); 2987544SN/A req->setThreadContext(id,0); 2997544SN/A } else { 3007544SN/A paddr &= ~((1 << access_size) - 1); 3018832SAli.Saidi@ARM.com req->setPhys(paddr, 1 << access_size, flags, masterId); 3027544SN/A req->setThreadContext(id,0); 3037544SN/A } 3047544SN/A assert(req->getSize() == 1); 3053187SN/A 3063187SN/A uint8_t *result = new uint8_t[8]; 3072SN/A 3082SN/A if (cmd < percentReads) { 3092SN/A // read 3101298SN/A 3114628SN/A // For now we only allow one outstanding request per address 3124628SN/A // per tester This means we assume CPU does write forwarding 3134628SN/A // to reads that alias something in the cpu store buffer. 3143282SN/A if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { 3154203SN/A delete [] result; 3163282SN/A delete req; 3173282SN/A return; 3183282SN/A } 3194628SN/A 3204628SN/A outstandingAddrs.insert(paddr); 3211298SN/A 3223187SN/A // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin 3238853Sandreas.hansson@arm.com funcProxy.readBlob(req->getPaddr(), result, req->getSize()); 3243187SN/A 3254628SN/A DPRINTF(MemTest, 3267657Ssteve.reinhardt@amd.com "id %d initiating %sread at addr %x (blk %x) expecting %x\n", 3277657Ssteve.reinhardt@amd.com id, do_functional ? "functional " : "", req->getPaddr(), 3287657Ssteve.reinhardt@amd.com blockAddr(req->getPaddr()), *result); 3293187SN/A 3308949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 3313187SN/A pkt->dataDynamicArray(new uint8_t[req->getSize()]); 3323187SN/A MemTestSenderState *state = new MemTestSenderState(result); 3333187SN/A pkt->senderState = state; 3343187SN/A 3357657Ssteve.reinhardt@amd.com if (do_functional) { 3368436SBrad.Beckmann@amd.com assert(pkt->needsResponse()); 3378436SBrad.Beckmann@amd.com pkt->setSuppressFuncError(); 3383187SN/A cachePort.sendFunctional(pkt); 3393204SN/A completeRequest(pkt); 340145SN/A } else { 3413262SN/A sendPkt(pkt); 342145SN/A } 3433187SN/A } else { 3442SN/A // write 3451298SN/A 3464628SN/A // For now we only allow one outstanding request per addreess 3474628SN/A // per tester. This means we assume CPU does write forwarding 3484628SN/A // to reads that alias something in the cpu store buffer. 3493282SN/A if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { 3503283SN/A delete [] result; 3513282SN/A delete req; 3523282SN/A return; 3533282SN/A } 3543282SN/A 3554628SN/A outstandingAddrs.insert(paddr); 3561298SN/A 3577657Ssteve.reinhardt@amd.com DPRINTF(MemTest, "initiating %swrite at addr %x (blk %x) value %x\n", 3587657Ssteve.reinhardt@amd.com do_functional ? "functional " : "", req->getPaddr(), 3597657Ssteve.reinhardt@amd.com blockAddr(req->getPaddr()), data & 0xff); 3604628SN/A 3618949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::WriteReq); 3623187SN/A uint8_t *pkt_data = new uint8_t[req->getSize()]; 3633187SN/A pkt->dataDynamicArray(pkt_data); 3643187SN/A memcpy(pkt_data, &data, req->getSize()); 3653187SN/A MemTestSenderState *state = new MemTestSenderState(result); 3663187SN/A pkt->senderState = state; 3673187SN/A 3687657Ssteve.reinhardt@amd.com if (do_functional) { 3698436SBrad.Beckmann@amd.com pkt->setSuppressFuncError(); 3703187SN/A cachePort.sendFunctional(pkt); 3713262SN/A completeRequest(pkt); 372145SN/A } else { 3733262SN/A sendPkt(pkt); 374145SN/A } 3753187SN/A } 3762SN/A} 3772SN/A 3782SN/Avoid 3793187SN/AMemTest::doRetry() 3802SN/A{ 3818975Sandreas.hansson@arm.com if (cachePort.sendTimingReq(retryPkt)) { 3827544SN/A DPRINTF(MemTest, "accessRetry setting to false\n"); 3833187SN/A accessRetry = false; 3843187SN/A retryPkt = NULL; 3853187SN/A } 3862SN/A} 3872SN/A 3885314SN/A 3895314SN/Avoid 3905314SN/AMemTest::printAddr(Addr a) 3915314SN/A{ 3925314SN/A cachePort.printAddr(a); 3935314SN/A} 3945315SN/A 3955315SN/A 3965315SN/AMemTest * 3975315SN/AMemTestParams::create() 3985315SN/A{ 3995315SN/A return new MemTest(this); 4005315SN/A} 401