memtest.cc revision 8949
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Erik Hallnor 292665SN/A * Steve Reinhardt 302SN/A */ 312SN/A 322SN/A// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded 332SN/A 341298SN/A#include <iomanip> 351298SN/A#include <set> 361259SN/A#include <string> 372SN/A#include <vector> 382SN/A 39146SN/A#include "base/misc.hh" 40146SN/A#include "base/statistics.hh" 417632SBrad.Beckmann@amd.com#include "cpu/testers/memtest/memtest.hh" 428232Snate@binkert.org#include "debug/MemTest.hh" 433348SN/A#include "mem/mem_object.hh" 448229Snate@binkert.org#include "mem/packet.hh" 453348SN/A#include "mem/port.hh" 463348SN/A#include "mem/request.hh" 4756SN/A#include "sim/sim_events.hh" 48695SN/A#include "sim/stats.hh" 498832SAli.Saidi@ARM.com#include "sim/system.hh" 502SN/A 512SN/Ausing namespace std; 522SN/A 531298SN/Aint TESTER_ALLOCATOR=0; 541298SN/A 553187SN/Abool 563349SN/AMemTest::CpuPort::recvTiming(PacketPtr pkt) 573187SN/A{ 588948Sandreas.hansson@arm.com assert(pkt->isResponse()); 598948Sandreas.hansson@arm.com memtest->completeRequest(pkt); 603187SN/A return true; 613187SN/A} 623187SN/A 633187SN/Avoid 643187SN/AMemTest::CpuPort::recvRetry() 653187SN/A{ 663187SN/A memtest->doRetry(); 673187SN/A} 683187SN/A 693262SN/Avoid 703349SN/AMemTest::sendPkt(PacketPtr pkt) { 713262SN/A if (atomic) { 723262SN/A cachePort.sendAtomic(pkt); 733262SN/A completeRequest(pkt); 743262SN/A } 753262SN/A else if (!cachePort.sendTiming(pkt)) { 767544SN/A DPRINTF(MemTest, "accessRetry setting to true\n"); 777544SN/A 787544SN/A // 797544SN/A // dma requests should never be retried 807544SN/A // 817544SN/A if (issueDmas) { 827544SN/A panic("Nacked DMA requests are not supported\n"); 837544SN/A } 843262SN/A accessRetry = true; 853262SN/A retryPkt = pkt; 867544SN/A } else { 877544SN/A if (issueDmas) { 887544SN/A dmaOutstanding = true; 897544SN/A } 903262SN/A } 913262SN/A 923262SN/A} 933262SN/A 945034SN/AMemTest::MemTest(const Params *p) 955034SN/A : MemObject(p), 962SN/A tickEvent(this), 973187SN/A cachePort("test", this), 983187SN/A funcPort("functional", this), 998853Sandreas.hansson@arm.com funcProxy(funcPort), 1003187SN/A retryPkt(NULL), 1013187SN/A// mainMem(main_mem), 1023187SN/A// checkMem(check_mem), 1035034SN/A size(p->memory_size), 1045034SN/A percentReads(p->percent_reads), 1055034SN/A percentFunctional(p->percent_functional), 1065034SN/A percentUncacheable(p->percent_uncacheable), 1077544SN/A issueDmas(p->issue_dmas), 1088832SAli.Saidi@ARM.com masterId(p->sys->getMasterId(name())), 1095034SN/A progressInterval(p->progress_interval), 1105034SN/A nextProgressMessage(p->progress_interval), 1115034SN/A percentSourceUnaligned(p->percent_source_unaligned), 1125034SN/A percentDestUnaligned(p->percent_dest_unaligned), 1135034SN/A maxLoads(p->max_loads), 1148436SBrad.Beckmann@amd.com atomic(p->atomic), 1158436SBrad.Beckmann@amd.com suppress_func_warnings(p->suppress_func_warnings) 1162SN/A{ 1177544SN/A id = TESTER_ALLOCATOR++; 1187544SN/A 1193187SN/A // Needs to be masked off once we know the block size. 1205034SN/A traceBlockAddr = p->trace_addr; 1212SN/A baseAddr1 = 0x100000; 1222SN/A baseAddr2 = 0x400000; 1232SN/A uncacheAddr = 0x800000; 1242SN/A 1252SN/A // set up counters 1262SN/A noResponseCycles = 0; 1272SN/A numReads = 0; 1288436SBrad.Beckmann@amd.com numWrites = 0; 1295606SN/A schedule(tickEvent, 0); 1301298SN/A 1313187SN/A accessRetry = false; 1327544SN/A dmaOutstanding = false; 1333187SN/A} 1343187SN/A 1358922Swilliam.wang@arm.comMasterPort & 1368922Swilliam.wang@arm.comMemTest::getMasterPort(const std::string &if_name, int idx) 1373187SN/A{ 1383187SN/A if (if_name == "functional") 1398922Swilliam.wang@arm.com return funcPort; 1403187SN/A else if (if_name == "test") 1418922Swilliam.wang@arm.com return cachePort; 1423187SN/A else 1438922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1443187SN/A} 1453187SN/A 1463187SN/Avoid 1473187SN/AMemTest::init() 1483187SN/A{ 1493187SN/A // By the time init() is called, the ports should be hooked up. 1503187SN/A blockSize = cachePort.peerBlockSize(); 1513187SN/A blockAddrMask = blockSize - 1; 1523187SN/A traceBlockAddr = blockAddr(traceBlockAddr); 1533187SN/A 1544579SN/A // initial memory contents for both physical memory and functional 1554579SN/A // memory should be 0; no need to initialize them. 1562SN/A} 1572SN/A 1582SN/A 1592SN/Avoid 1603349SN/AMemTest::completeRequest(PacketPtr pkt) 1612SN/A{ 1624628SN/A Request *req = pkt->req; 1634628SN/A 1647544SN/A if (issueDmas) { 1657544SN/A dmaOutstanding = false; 1667544SN/A } 1677544SN/A 1688436SBrad.Beckmann@amd.com DPRINTF(MemTest, "completing %s at address %x (blk %x) %s\n", 1694628SN/A pkt->isWrite() ? "write" : "read", 1708436SBrad.Beckmann@amd.com req->getPaddr(), blockAddr(req->getPaddr()), 1718436SBrad.Beckmann@amd.com pkt->isError() ? "error" : "success"); 1724628SN/A 1733187SN/A MemTestSenderState *state = 1743187SN/A dynamic_cast<MemTestSenderState *>(pkt->senderState); 1753187SN/A 1763187SN/A uint8_t *data = state->data; 1773187SN/A uint8_t *pkt_data = pkt->getPtr<uint8_t>(); 1783187SN/A 1791298SN/A //Remove the address from the list of outstanding 1804628SN/A std::set<unsigned>::iterator removeAddr = 1814628SN/A outstandingAddrs.find(req->getPaddr()); 1821298SN/A assert(removeAddr != outstandingAddrs.end()); 1831298SN/A outstandingAddrs.erase(removeAddr); 1841298SN/A 1858436SBrad.Beckmann@amd.com if (pkt->isError()) { 1868436SBrad.Beckmann@amd.com if (!suppress_func_warnings) { 1878436SBrad.Beckmann@amd.com warn("Functional Access failed for %x at %x\n", 1888436SBrad.Beckmann@amd.com pkt->isWrite() ? "write" : "read", req->getPaddr()); 1892SN/A } 1908436SBrad.Beckmann@amd.com } else { 1918436SBrad.Beckmann@amd.com if (pkt->isRead()) { 1928436SBrad.Beckmann@amd.com if (memcmp(pkt_data, data, pkt->getSize()) != 0) { 1938436SBrad.Beckmann@amd.com panic("%s: read of %x (blk %x) @ cycle %d " 1948436SBrad.Beckmann@amd.com "returns %x, expected %x\n", name(), 1958436SBrad.Beckmann@amd.com req->getPaddr(), blockAddr(req->getPaddr()), curTick(), 1968436SBrad.Beckmann@amd.com *pkt_data, *data); 1978436SBrad.Beckmann@amd.com } 1982SN/A 1998436SBrad.Beckmann@amd.com numReads++; 2008436SBrad.Beckmann@amd.com numReadsStat++; 2012SN/A 2028436SBrad.Beckmann@amd.com if (numReads == (uint64_t)nextProgressMessage) { 2038436SBrad.Beckmann@amd.com ccprintf(cerr, "%s: completed %d read, %d write accesses @%d\n", 2048436SBrad.Beckmann@amd.com name(), numReads, numWrites, curTick()); 2058436SBrad.Beckmann@amd.com nextProgressMessage += progressInterval; 2068436SBrad.Beckmann@amd.com } 2078436SBrad.Beckmann@amd.com 2088436SBrad.Beckmann@amd.com if (maxLoads != 0 && numReads >= maxLoads) 2098436SBrad.Beckmann@amd.com exitSimLoop("maximum number of loads reached"); 2108436SBrad.Beckmann@amd.com } else { 2118436SBrad.Beckmann@amd.com assert(pkt->isWrite()); 2128853Sandreas.hansson@arm.com funcProxy.writeBlob(req->getPaddr(), pkt_data, req->getSize()); 2138436SBrad.Beckmann@amd.com numWrites++; 2148436SBrad.Beckmann@amd.com numWritesStat++; 2152SN/A } 2162SN/A } 2172SN/A 2182SN/A noResponseCycles = 0; 2193187SN/A delete state; 2202SN/A delete [] data; 2213187SN/A delete pkt->req; 2223187SN/A delete pkt; 2232SN/A} 2242SN/A 2252SN/Avoid 2262SN/AMemTest::regStats() 2272SN/A{ 228729SN/A using namespace Stats; 2292SN/A 230695SN/A numReadsStat 2312SN/A .name(name() + ".num_reads") 2322SN/A .desc("number of read accesses completed") 2332SN/A ; 2342SN/A 235695SN/A numWritesStat 2362SN/A .name(name() + ".num_writes") 2372SN/A .desc("number of write accesses completed") 2382SN/A ; 2392SN/A 240695SN/A numCopiesStat 2412SN/A .name(name() + ".num_copies") 2422SN/A .desc("number of copy accesses completed") 2432SN/A ; 2442SN/A} 2452SN/A 2462SN/Avoid 2472SN/AMemTest::tick() 2482SN/A{ 2492SN/A if (!tickEvent.scheduled()) 2507823Ssteve.reinhardt@amd.com schedule(tickEvent, curTick() + ticks(1)); 2512SN/A 2521298SN/A if (++noResponseCycles >= 500000) { 2537544SN/A if (issueDmas) { 2547544SN/A cerr << "DMA tester "; 2557544SN/A } 2567823Ssteve.reinhardt@amd.com cerr << name() << ": deadlocked at cycle " << curTick() << endl; 2572SN/A fatal(""); 2582SN/A } 2592SN/A 2607544SN/A if (accessRetry || (issueDmas && dmaOutstanding)) { 2617544SN/A DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n"); 2622SN/A return; 2632SN/A } 2642SN/A 2652SN/A //make new request 2661899SN/A unsigned cmd = random() % 100; 2671899SN/A unsigned offset = random() % size; 2682SN/A unsigned base = random() % 2; 2692SN/A uint64_t data = random(); 2702SN/A unsigned access_size = random() % 4; 2715736SN/A bool uncacheable = (random() % 100) < percentUncacheable; 2722SN/A 2737544SN/A unsigned dma_access_size = random() % 4; 2747544SN/A 2751298SN/A //If we aren't doing copies, use id as offset, and do a false sharing 2761298SN/A //mem tester 2773187SN/A //We can eliminate the lower bits of the offset, and then use the id 2783187SN/A //to offset within the blks 2794628SN/A offset = blockAddr(offset); 2803187SN/A offset += id; 2813187SN/A access_size = 0; 2827544SN/A dma_access_size = 0; 2831298SN/A 2843187SN/A Request *req = new Request(); 2855736SN/A Request::Flags flags; 2863187SN/A Addr paddr; 2872SN/A 2885736SN/A if (uncacheable) { 2895736SN/A flags.set(Request::UNCACHEABLE); 2903187SN/A paddr = uncacheAddr + offset; 2917544SN/A } else { 2923187SN/A paddr = ((base) ? baseAddr1 : baseAddr2) + offset; 2932SN/A } 2947657Ssteve.reinhardt@amd.com bool do_functional = (random() % 100 < percentFunctional) && !uncacheable; 2952SN/A 2967544SN/A if (issueDmas) { 2977544SN/A paddr &= ~((1 << dma_access_size) - 1); 2988832SAli.Saidi@ARM.com req->setPhys(paddr, 1 << dma_access_size, flags, masterId); 2997544SN/A req->setThreadContext(id,0); 3007544SN/A } else { 3017544SN/A paddr &= ~((1 << access_size) - 1); 3028832SAli.Saidi@ARM.com req->setPhys(paddr, 1 << access_size, flags, masterId); 3037544SN/A req->setThreadContext(id,0); 3047544SN/A } 3057544SN/A assert(req->getSize() == 1); 3063187SN/A 3073187SN/A uint8_t *result = new uint8_t[8]; 3082SN/A 3092SN/A if (cmd < percentReads) { 3102SN/A // read 3111298SN/A 3124628SN/A // For now we only allow one outstanding request per address 3134628SN/A // per tester This means we assume CPU does write forwarding 3144628SN/A // to reads that alias something in the cpu store buffer. 3153282SN/A if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { 3164203SN/A delete [] result; 3173282SN/A delete req; 3183282SN/A return; 3193282SN/A } 3204628SN/A 3214628SN/A outstandingAddrs.insert(paddr); 3221298SN/A 3233187SN/A // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin 3248853Sandreas.hansson@arm.com funcProxy.readBlob(req->getPaddr(), result, req->getSize()); 3253187SN/A 3264628SN/A DPRINTF(MemTest, 3277657Ssteve.reinhardt@amd.com "id %d initiating %sread at addr %x (blk %x) expecting %x\n", 3287657Ssteve.reinhardt@amd.com id, do_functional ? "functional " : "", req->getPaddr(), 3297657Ssteve.reinhardt@amd.com blockAddr(req->getPaddr()), *result); 3303187SN/A 3318949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 3323187SN/A pkt->dataDynamicArray(new uint8_t[req->getSize()]); 3333187SN/A MemTestSenderState *state = new MemTestSenderState(result); 3343187SN/A pkt->senderState = state; 3353187SN/A 3367657Ssteve.reinhardt@amd.com if (do_functional) { 3378436SBrad.Beckmann@amd.com assert(pkt->needsResponse()); 3388436SBrad.Beckmann@amd.com pkt->setSuppressFuncError(); 3393187SN/A cachePort.sendFunctional(pkt); 3403204SN/A completeRequest(pkt); 341145SN/A } else { 3423262SN/A sendPkt(pkt); 343145SN/A } 3443187SN/A } else { 3452SN/A // write 3461298SN/A 3474628SN/A // For now we only allow one outstanding request per addreess 3484628SN/A // per tester. This means we assume CPU does write forwarding 3494628SN/A // to reads that alias something in the cpu store buffer. 3503282SN/A if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { 3513283SN/A delete [] result; 3523282SN/A delete req; 3533282SN/A return; 3543282SN/A } 3553282SN/A 3564628SN/A outstandingAddrs.insert(paddr); 3571298SN/A 3587657Ssteve.reinhardt@amd.com DPRINTF(MemTest, "initiating %swrite at addr %x (blk %x) value %x\n", 3597657Ssteve.reinhardt@amd.com do_functional ? "functional " : "", req->getPaddr(), 3607657Ssteve.reinhardt@amd.com blockAddr(req->getPaddr()), data & 0xff); 3614628SN/A 3628949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::WriteReq); 3633187SN/A uint8_t *pkt_data = new uint8_t[req->getSize()]; 3643187SN/A pkt->dataDynamicArray(pkt_data); 3653187SN/A memcpy(pkt_data, &data, req->getSize()); 3663187SN/A MemTestSenderState *state = new MemTestSenderState(result); 3673187SN/A pkt->senderState = state; 3683187SN/A 3697657Ssteve.reinhardt@amd.com if (do_functional) { 3708436SBrad.Beckmann@amd.com pkt->setSuppressFuncError(); 3713187SN/A cachePort.sendFunctional(pkt); 3723262SN/A completeRequest(pkt); 373145SN/A } else { 3743262SN/A sendPkt(pkt); 375145SN/A } 3763187SN/A } 3772SN/A} 3782SN/A 3792SN/Avoid 3803187SN/AMemTest::doRetry() 3812SN/A{ 3823187SN/A if (cachePort.sendTiming(retryPkt)) { 3837544SN/A DPRINTF(MemTest, "accessRetry setting to false\n"); 3843187SN/A accessRetry = false; 3853187SN/A retryPkt = NULL; 3863187SN/A } 3872SN/A} 3882SN/A 3895314SN/A 3905314SN/Avoid 3915314SN/AMemTest::printAddr(Addr a) 3925314SN/A{ 3935314SN/A cachePort.printAddr(a); 3945314SN/A} 3955315SN/A 3965315SN/A 3975315SN/AMemTest * 3985315SN/AMemTestParams::create() 3995315SN/A{ 4005315SN/A return new MemTest(this); 4015315SN/A} 402