memtest.cc revision 6227
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 * Steve Reinhardt 30 */ 31 32// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded 33 34#include <iomanip> 35#include <set> 36#include <string> 37#include <vector> 38 39#include "base/misc.hh" 40#include "base/statistics.hh" 41#include "cpu/memtest/memtest.hh" 42#include "mem/mem_object.hh" 43#include "mem/port.hh" 44#include "mem/packet.hh" 45#include "mem/request.hh" 46#include "sim/sim_events.hh" 47#include "sim/stats.hh" 48 49using namespace std; 50 51int TESTER_ALLOCATOR=0; 52 53bool 54MemTest::CpuPort::recvTiming(PacketPtr pkt) 55{ 56 if (pkt->isResponse()) { 57 memtest->completeRequest(pkt); 58 } else { 59 // must be snoop upcall 60 assert(pkt->isRequest()); 61 assert(pkt->getDest() == Packet::Broadcast); 62 } 63 return true; 64} 65 66Tick 67MemTest::CpuPort::recvAtomic(PacketPtr pkt) 68{ 69 // must be snoop upcall 70 assert(pkt->isRequest()); 71 assert(pkt->getDest() == Packet::Broadcast); 72 return curTick; 73} 74 75void 76MemTest::CpuPort::recvFunctional(PacketPtr pkt) 77{ 78 //Do nothing if we see one come through 79// if (curTick != 0)//Supress warning durring initialization 80// warn("Functional Writes not implemented in MemTester\n"); 81 //Need to find any response values that intersect and update 82 return; 83} 84 85void 86MemTest::CpuPort::recvStatusChange(Status status) 87{ 88 if (status == RangeChange) { 89 if (!snoopRangeSent) { 90 snoopRangeSent = true; 91 sendStatusChange(Port::RangeChange); 92 } 93 return; 94 } 95 96 panic("MemTest doesn't expect recvStatusChange callback!"); 97} 98 99void 100MemTest::CpuPort::recvRetry() 101{ 102 memtest->doRetry(); 103} 104 105void 106MemTest::sendPkt(PacketPtr pkt) { 107 if (atomic) { 108 cachePort.sendAtomic(pkt); 109 completeRequest(pkt); 110 } 111 else if (!cachePort.sendTiming(pkt)) { 112 accessRetry = true; 113 retryPkt = pkt; 114 } 115 116} 117 118MemTest::MemTest(const Params *p) 119 : MemObject(p), 120 tickEvent(this), 121 cachePort("test", this), 122 funcPort("functional", this), 123 retryPkt(NULL), 124// mainMem(main_mem), 125// checkMem(check_mem), 126 size(p->memory_size), 127 percentReads(p->percent_reads), 128 percentFunctional(p->percent_functional), 129 percentUncacheable(p->percent_uncacheable), 130 progressInterval(p->progress_interval), 131 nextProgressMessage(p->progress_interval), 132 percentSourceUnaligned(p->percent_source_unaligned), 133 percentDestUnaligned(p->percent_dest_unaligned), 134 maxLoads(p->max_loads), 135 atomic(p->atomic) 136{ 137 vector<string> cmd; 138 cmd.push_back("/bin/ls"); 139 vector<string> null_vec; 140 // thread = new SimpleThread(NULL, 0, NULL, 0, mainMem); 141 curTick = 0; 142 143 cachePort.snoopRangeSent = false; 144 funcPort.snoopRangeSent = true; 145 146 // Needs to be masked off once we know the block size. 147 traceBlockAddr = p->trace_addr; 148 baseAddr1 = 0x100000; 149 baseAddr2 = 0x400000; 150 uncacheAddr = 0x800000; 151 152 // set up counters 153 noResponseCycles = 0; 154 numReads = 0; 155 schedule(tickEvent, 0); 156 157 id = TESTER_ALLOCATOR++; 158 159 accessRetry = false; 160} 161 162Port * 163MemTest::getPort(const std::string &if_name, int idx) 164{ 165 if (if_name == "functional") 166 return &funcPort; 167 else if (if_name == "test") 168 return &cachePort; 169 else 170 panic("No Such Port\n"); 171} 172 173void 174MemTest::init() 175{ 176 // By the time init() is called, the ports should be hooked up. 177 blockSize = cachePort.peerBlockSize(); 178 blockAddrMask = blockSize - 1; 179 traceBlockAddr = blockAddr(traceBlockAddr); 180 181 // initial memory contents for both physical memory and functional 182 // memory should be 0; no need to initialize them. 183} 184 185 186void 187MemTest::completeRequest(PacketPtr pkt) 188{ 189 Request *req = pkt->req; 190 191 DPRINTF(MemTest, "completing %s at address %x (blk %x)\n", 192 pkt->isWrite() ? "write" : "read", 193 req->getPaddr(), blockAddr(req->getPaddr())); 194 195 MemTestSenderState *state = 196 dynamic_cast<MemTestSenderState *>(pkt->senderState); 197 198 uint8_t *data = state->data; 199 uint8_t *pkt_data = pkt->getPtr<uint8_t>(); 200 201 //Remove the address from the list of outstanding 202 std::set<unsigned>::iterator removeAddr = 203 outstandingAddrs.find(req->getPaddr()); 204 assert(removeAddr != outstandingAddrs.end()); 205 outstandingAddrs.erase(removeAddr); 206 207 assert(pkt->isResponse()); 208 209 if (pkt->isRead()) { 210 if (memcmp(pkt_data, data, pkt->getSize()) != 0) { 211 panic("%s: read of %x (blk %x) @ cycle %d " 212 "returns %x, expected %x\n", name(), 213 req->getPaddr(), blockAddr(req->getPaddr()), curTick, 214 *pkt_data, *data); 215 } 216 217 numReads++; 218 numReadsStat++; 219 220 if (numReads == (uint64_t)nextProgressMessage) { 221 ccprintf(cerr, "%s: completed %d read accesses @%d\n", 222 name(), numReads, curTick); 223 nextProgressMessage += progressInterval; 224 } 225 226 if (maxLoads != 0 && numReads >= maxLoads) 227 exitSimLoop("maximum number of loads reached"); 228 } else { 229 assert(pkt->isWrite()); 230 numWritesStat++; 231 } 232 233 noResponseCycles = 0; 234 delete state; 235 delete [] data; 236 delete pkt->req; 237 delete pkt; 238} 239 240void 241MemTest::regStats() 242{ 243 using namespace Stats; 244 245 numReadsStat 246 .name(name() + ".num_reads") 247 .desc("number of read accesses completed") 248 ; 249 250 numWritesStat 251 .name(name() + ".num_writes") 252 .desc("number of write accesses completed") 253 ; 254 255 numCopiesStat 256 .name(name() + ".num_copies") 257 .desc("number of copy accesses completed") 258 ; 259} 260 261void 262MemTest::tick() 263{ 264 if (!tickEvent.scheduled()) 265 schedule(tickEvent, curTick + ticks(1)); 266 267 if (++noResponseCycles >= 500000) { 268 cerr << name() << ": deadlocked at cycle " << curTick << endl; 269 fatal(""); 270 } 271 272 if (accessRetry) { 273 return; 274 } 275 276 //make new request 277 unsigned cmd = random() % 100; 278 unsigned offset = random() % size; 279 unsigned base = random() % 2; 280 uint64_t data = random(); 281 unsigned access_size = random() % 4; 282 bool uncacheable = (random() % 100) < percentUncacheable; 283 284 //If we aren't doing copies, use id as offset, and do a false sharing 285 //mem tester 286 //We can eliminate the lower bits of the offset, and then use the id 287 //to offset within the blks 288 offset = blockAddr(offset); 289 offset += id; 290 access_size = 0; 291 292 Request *req = new Request(); 293 Request::Flags flags; 294 Addr paddr; 295 296 if (uncacheable) { 297 flags.set(Request::UNCACHEABLE); 298 paddr = uncacheAddr + offset; 299 } else { 300 paddr = ((base) ? baseAddr1 : baseAddr2) + offset; 301 } 302 bool probe = (random() % 100 < percentFunctional) && !uncacheable; 303 304 paddr &= ~((1 << access_size) - 1); 305 req->setPhys(paddr, 1 << access_size, flags); 306 req->setThreadContext(id,0); 307 308 uint8_t *result = new uint8_t[8]; 309 310 if (cmd < percentReads) { 311 // read 312 313 // For now we only allow one outstanding request per address 314 // per tester This means we assume CPU does write forwarding 315 // to reads that alias something in the cpu store buffer. 316 if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { 317 delete [] result; 318 delete req; 319 return; 320 } 321 322 outstandingAddrs.insert(paddr); 323 324 // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin 325 funcPort.readBlob(req->getPaddr(), result, req->getSize()); 326 327 DPRINTF(MemTest, 328 "initiating read at address %x (blk %x) expecting %x\n", 329 req->getPaddr(), blockAddr(req->getPaddr()), *result); 330 331 PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); 332 pkt->setSrc(0); 333 pkt->dataDynamicArray(new uint8_t[req->getSize()]); 334 MemTestSenderState *state = new MemTestSenderState(result); 335 pkt->senderState = state; 336 337 if (probe) { 338 cachePort.sendFunctional(pkt); 339 completeRequest(pkt); 340 } else { 341 sendPkt(pkt); 342 } 343 } else { 344 // write 345 346 // For now we only allow one outstanding request per addreess 347 // per tester. This means we assume CPU does write forwarding 348 // to reads that alias something in the cpu store buffer. 349 if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { 350 delete [] result; 351 delete req; 352 return; 353 } 354 355 outstandingAddrs.insert(paddr); 356 357 DPRINTF(MemTest, "initiating write at address %x (blk %x) value %x\n", 358 req->getPaddr(), blockAddr(req->getPaddr()), data & 0xff); 359 360 PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast); 361 pkt->setSrc(0); 362 uint8_t *pkt_data = new uint8_t[req->getSize()]; 363 pkt->dataDynamicArray(pkt_data); 364 memcpy(pkt_data, &data, req->getSize()); 365 MemTestSenderState *state = new MemTestSenderState(result); 366 pkt->senderState = state; 367 368 funcPort.writeBlob(req->getPaddr(), pkt_data, req->getSize()); 369 370 if (probe) { 371 cachePort.sendFunctional(pkt); 372 completeRequest(pkt); 373 } else { 374 sendPkt(pkt); 375 } 376 } 377} 378 379void 380MemTest::doRetry() 381{ 382 if (cachePort.sendTiming(retryPkt)) { 383 accessRetry = false; 384 retryPkt = NULL; 385 } 386} 387 388 389void 390MemTest::printAddr(Addr a) 391{ 392 cachePort.printAddr(a); 393} 394 395 396MemTest * 397MemTestParams::create() 398{ 399 return new MemTest(this); 400} 401