memtest.cc revision 4579 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Steve Reinhardt
30 */
31
32// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
33
34#include <iomanip>
35#include <set>
36#include <string>
37#include <vector>
38
39#include "base/misc.hh"
40#include "base/statistics.hh"
41#include "cpu/memtest/memtest.hh"
42//#include "cpu/simple_thread.hh"
43//#include "mem/cache/base_cache.hh"
44#include "mem/mem_object.hh"
45#include "mem/port.hh"
46#include "mem/packet.hh"
47//#include "mem/physical.hh"
48#include "mem/request.hh"
49#include "sim/builder.hh"
50#include "sim/sim_events.hh"
51#include "sim/stats.hh"
52
53using namespace std;
54
55int TESTER_ALLOCATOR=0;
56
57bool
58MemTest::CpuPort::recvTiming(PacketPtr pkt)
59{
60    memtest->completeRequest(pkt);
61    return true;
62}
63
64Tick
65MemTest::CpuPort::recvAtomic(PacketPtr pkt)
66{
67    panic("MemTest doesn't expect recvAtomic callback!");
68    return curTick;
69}
70
71void
72MemTest::CpuPort::recvFunctional(PacketPtr pkt)
73{
74    //Do nothing if we see one come through
75//    if (curTick != 0)//Supress warning durring initialization
76//        warn("Functional Writes not implemented in MemTester\n");
77    //Need to find any response values that intersect and update
78    return;
79}
80
81void
82MemTest::CpuPort::recvStatusChange(Status status)
83{
84    if (status == RangeChange) {
85        if (!snoopRangeSent) {
86            snoopRangeSent = true;
87            sendStatusChange(Port::RangeChange);
88        }
89        return;
90    }
91
92    panic("MemTest doesn't expect recvStatusChange callback!");
93}
94
95void
96MemTest::CpuPort::recvRetry()
97{
98    memtest->doRetry();
99}
100
101void
102MemTest::sendPkt(PacketPtr pkt) {
103    if (atomic) {
104        cachePort.sendAtomic(pkt);
105        pkt->makeAtomicResponse();
106        completeRequest(pkt);
107    }
108    else if (!cachePort.sendTiming(pkt)) {
109        accessRetry = true;
110        retryPkt = pkt;
111    }
112
113}
114
115MemTest::MemTest(const string &name,
116//		 MemInterface *_cache_interface,
117//		 PhysicalMemory *main_mem,
118//		 PhysicalMemory *check_mem,
119                 unsigned _memorySize,
120                 unsigned _percentReads,
121                 unsigned _percentFunctional,
122                 unsigned _percentUncacheable,
123                 unsigned _progressInterval,
124                 unsigned _percentSourceUnaligned,
125                 unsigned _percentDestUnaligned,
126                 Addr _traceAddr,
127                 Counter _max_loads,
128                 bool _atomic)
129    : MemObject(name),
130      tickEvent(this),
131      cachePort("test", this),
132      funcPort("functional", this),
133      retryPkt(NULL),
134//      mainMem(main_mem),
135//      checkMem(check_mem),
136      size(_memorySize),
137      percentReads(_percentReads),
138      percentFunctional(_percentFunctional),
139      percentUncacheable(_percentUncacheable),
140      progressInterval(_progressInterval),
141      nextProgressMessage(_progressInterval),
142      percentSourceUnaligned(_percentSourceUnaligned),
143      percentDestUnaligned(percentDestUnaligned),
144      maxLoads(_max_loads),
145      atomic(_atomic)
146{
147    vector<string> cmd;
148    cmd.push_back("/bin/ls");
149    vector<string> null_vec;
150    //  thread = new SimpleThread(NULL, 0, NULL, 0, mainMem);
151    curTick = 0;
152
153    cachePort.snoopRangeSent = false;
154    funcPort.snoopRangeSent = true;
155
156    // Needs to be masked off once we know the block size.
157    traceBlockAddr = _traceAddr;
158    baseAddr1 = 0x100000;
159    baseAddr2 = 0x400000;
160    uncacheAddr = 0x800000;
161
162    // set up counters
163    noResponseCycles = 0;
164    numReads = 0;
165    tickEvent.schedule(0);
166
167    id = TESTER_ALLOCATOR++;
168    if (TESTER_ALLOCATOR > 8)
169        panic("False sharing memtester only allows up to 8 testers");
170
171    accessRetry = false;
172}
173
174Port *
175MemTest::getPort(const std::string &if_name, int idx)
176{
177    if (if_name == "functional")
178        return &funcPort;
179    else if (if_name == "test")
180        return &cachePort;
181    else
182        panic("No Such Port\n");
183}
184
185void
186MemTest::init()
187{
188    // By the time init() is called, the ports should be hooked up.
189    blockSize = cachePort.peerBlockSize();
190    blockAddrMask = blockSize - 1;
191    traceBlockAddr = blockAddr(traceBlockAddr);
192
193    // initial memory contents for both physical memory and functional
194    // memory should be 0; no need to initialize them.
195}
196
197static void
198printData(ostream &os, uint8_t *data, int nbytes)
199{
200    os << hex << setfill('0');
201    // assume little-endian: print bytes from highest address to lowest
202    for (uint8_t *dp = data + nbytes - 1; dp >= data; --dp) {
203        os << setw(2) << (unsigned)*dp;
204    }
205    os << dec;
206}
207
208void
209MemTest::completeRequest(PacketPtr pkt)
210{
211    MemTestSenderState *state =
212        dynamic_cast<MemTestSenderState *>(pkt->senderState);
213
214    uint8_t *data = state->data;
215    uint8_t *pkt_data = pkt->getPtr<uint8_t>();
216    Request *req = pkt->req;
217
218    //Remove the address from the list of outstanding
219    std::set<unsigned>::iterator removeAddr = outstandingAddrs.find(req->getPaddr());
220    assert(removeAddr != outstandingAddrs.end());
221    outstandingAddrs.erase(removeAddr);
222
223    switch (pkt->cmd.toInt()) {
224      case MemCmd::ReadResp:
225
226        if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
227            cerr << name() << ": on read of 0x" << hex << req->getPaddr()
228                 << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
229                 << "@ cycle " << dec << curTick
230                 << ", cache returns 0x";
231            printData(cerr, pkt_data, pkt->getSize());
232            cerr << ", expected 0x";
233            printData(cerr, data, pkt->getSize());
234            cerr << endl;
235            fatal("");
236        }
237
238        numReads++;
239        numReadsStat++;
240
241        if (numReads == nextProgressMessage) {
242            ccprintf(cerr, "%s: completed %d read accesses @%d\n",
243                     name(), numReads, curTick);
244            nextProgressMessage += progressInterval;
245        }
246
247        if (numReads >= maxLoads)
248            exitSimLoop("Maximum number of loads reached!");
249        break;
250
251      case MemCmd::WriteResp:
252        numWritesStat++;
253        break;
254/*
255      case Copy:
256        //Also remove dest from outstanding list
257        removeAddr = outstandingAddrs.find(req->dest);
258        assert(removeAddr != outstandingAddrs.end());
259        outstandingAddrs.erase(removeAddr);
260        numCopiesStat++;
261        break;
262*/
263      default:
264        panic("invalid command %s (%d)", pkt->cmdString(), pkt->cmd.toInt());
265    }
266
267    if (blockAddr(req->getPaddr()) == traceBlockAddr) {
268        cerr << name() << ": completed "
269             << (pkt->isWrite() ? "write" : "read")
270             << " access of "
271             << dec << pkt->getSize() << " bytes at address 0x"
272             << hex << req->getPaddr()
273             << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
274             << ", value = 0x";
275        printData(cerr, pkt_data, pkt->getSize());
276        cerr << " @ cycle " << dec << curTick;
277
278        cerr << endl;
279    }
280
281    noResponseCycles = 0;
282    delete state;
283    delete [] data;
284    delete pkt->req;
285    delete pkt;
286}
287
288void
289MemTest::regStats()
290{
291    using namespace Stats;
292
293    numReadsStat
294        .name(name() + ".num_reads")
295        .desc("number of read accesses completed")
296        ;
297
298    numWritesStat
299        .name(name() + ".num_writes")
300        .desc("number of write accesses completed")
301        ;
302
303    numCopiesStat
304        .name(name() + ".num_copies")
305        .desc("number of copy accesses completed")
306        ;
307}
308
309void
310MemTest::tick()
311{
312    if (!tickEvent.scheduled())
313        tickEvent.schedule(curTick + cycles(1));
314
315    if (++noResponseCycles >= 500000) {
316        cerr << name() << ": deadlocked at cycle " << curTick << endl;
317        fatal("");
318    }
319
320    if (accessRetry) {
321        return;
322    }
323
324    //make new request
325    unsigned cmd = random() % 100;
326    unsigned offset = random() % size;
327    unsigned base = random() % 2;
328    uint64_t data = random();
329    unsigned access_size = random() % 4;
330    unsigned cacheable = random() % 100;
331
332    //If we aren't doing copies, use id as offset, and do a false sharing
333    //mem tester
334    //We can eliminate the lower bits of the offset, and then use the id
335    //to offset within the blks
336    offset &= ~63; //Not the low order bits
337    offset += id;
338    access_size = 0;
339
340    Request *req = new Request();
341    uint32_t flags = 0;
342    Addr paddr;
343
344    if (cacheable < percentUncacheable) {
345        flags |= UNCACHEABLE;
346        paddr = uncacheAddr + offset;
347    } else {
348        paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
349    }
350    bool probe = (random() % 100 < percentFunctional) && !(flags & UNCACHEABLE);
351    //bool probe = false;
352
353    paddr &= ~((1 << access_size) - 1);
354    req->setPhys(paddr, 1 << access_size, flags);
355    req->setThreadContext(id,0);
356
357    uint8_t *result = new uint8_t[8];
358
359    if (cmd < percentReads) {
360        // read
361
362        //For now we only allow one outstanding request per addreess per tester
363        //This means we assume CPU does write forwarding to reads that alias something
364        //in the cpu store buffer.
365        if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
366            delete [] result;
367            delete req;
368            return;
369        }
370        else outstandingAddrs.insert(paddr);
371
372        // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
373        funcPort.readBlob(req->getPaddr(), result, req->getSize());
374
375        if (blockAddr(paddr) == traceBlockAddr) {
376            cerr << name()
377                 << ": initiating read "
378                 << ((probe) ? "probe of " : "access of ")
379                 << dec << req->getSize() << " bytes from addr 0x"
380                 << hex << paddr
381                 << " (0x" << hex << blockAddr(paddr) << ")"
382                 << " at cycle "
383                 << dec << curTick << endl;
384        }
385
386        PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
387        pkt->dataDynamicArray(new uint8_t[req->getSize()]);
388        MemTestSenderState *state = new MemTestSenderState(result);
389        pkt->senderState = state;
390
391        if (probe) {
392            cachePort.sendFunctional(pkt);
393            pkt->makeAtomicResponse();
394            completeRequest(pkt);
395        } else {
396//	    req->completionEvent = new MemCompleteEvent(req, result, this);
397            sendPkt(pkt);
398        }
399    } else {
400        // write
401
402        //For now we only allow one outstanding request per addreess per tester
403        //This means we assume CPU does write forwarding to reads that alias something
404        //in the cpu store buffer.
405        if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
406            delete [] result;
407            delete req;
408            return;
409        }
410
411        else outstandingAddrs.insert(paddr);
412
413/*
414        if (blockAddr(req->getPaddr()) == traceBlockAddr) {
415            cerr << name() << ": initiating write "
416                 << ((probe)?"probe of ":"access of ")
417                 << dec << req->getSize() << " bytes (value = 0x";
418            printData(cerr, data_pkt->getPtr(), req->getSize());
419            cerr << ") to addr 0x"
420                 << hex << req->getPaddr()
421                 << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
422                 << " at cycle "
423                 << dec << curTick << endl;
424        }
425*/
426        PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
427        uint8_t *pkt_data = new uint8_t[req->getSize()];
428        pkt->dataDynamicArray(pkt_data);
429        memcpy(pkt_data, &data, req->getSize());
430        MemTestSenderState *state = new MemTestSenderState(result);
431        pkt->senderState = state;
432
433        funcPort.writeBlob(req->getPaddr(), pkt_data, req->getSize());
434
435        if (probe) {
436            cachePort.sendFunctional(pkt);
437            pkt->makeAtomicResponse();
438            completeRequest(pkt);
439        } else {
440//	    req->completionEvent = new MemCompleteEvent(req, NULL, this);
441            sendPkt(pkt);
442        }
443    }
444/*    else {
445        // copy
446        unsigned source_align = random() % 100;
447        unsigned dest_align = random() % 100;
448        unsigned offset2 = random() % size;
449
450        Addr source = ((base) ? baseAddr1 : baseAddr2) + offset;
451        Addr dest = ((base) ? baseAddr2 : baseAddr1) + offset2;
452        if (outstandingAddrs.find(source) != outstandingAddrs.end()) return;
453        else outstandingAddrs.insert(source);
454        if (outstandingAddrs.find(dest) != outstandingAddrs.end()) return;
455        else outstandingAddrs.insert(dest);
456
457        if (source_align >= percentSourceUnaligned) {
458            source = blockAddr(source);
459        }
460        if (dest_align >= percentDestUnaligned) {
461            dest = blockAddr(dest);
462        }
463        req->cmd = Copy;
464        req->flags &= ~UNCACHEABLE;
465        req->paddr = source;
466        req->dest = dest;
467        delete [] req->data;
468        req->data = new uint8_t[blockSize];
469        req->size = blockSize;
470        if (source == traceBlockAddr || dest == traceBlockAddr) {
471            cerr << name()
472                 << ": initiating copy of "
473                 << dec << req->size << " bytes from addr 0x"
474                 << hex << source
475                 << " (0x" << hex << blockAddr(source) << ")"
476                 << " to addr 0x"
477                 << hex << dest
478                 << " (0x" << hex << blockAddr(dest) << ")"
479                 << " at cycle "
480                 << dec << curTick << endl;
481        }*
482        cacheInterface->access(req);
483        uint8_t result[blockSize];
484        checkMem->access(Read, source, &result, blockSize);
485        checkMem->access(Write, dest, &result, blockSize);
486    }
487*/
488}
489
490void
491MemTest::doRetry()
492{
493    if (cachePort.sendTiming(retryPkt)) {
494        accessRetry = false;
495        retryPkt = NULL;
496    }
497}
498
499BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
500
501//    SimObjectParam<BaseCache *> cache;
502//    SimObjectParam<PhysicalMemory *> main_mem;
503//    SimObjectParam<PhysicalMemory *> check_mem;
504    Param<unsigned> memory_size;
505    Param<unsigned> percent_reads;
506    Param<unsigned> percent_functional;
507    Param<unsigned> percent_uncacheable;
508    Param<unsigned> progress_interval;
509    Param<unsigned> percent_source_unaligned;
510    Param<unsigned> percent_dest_unaligned;
511    Param<Addr> trace_addr;
512    Param<Counter> max_loads;
513    Param<bool> atomic;
514
515END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
516
517
518BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
519
520//    INIT_PARAM(cache, "L1 cache"),
521//    INIT_PARAM(main_mem, "hierarchical memory"),
522//    INIT_PARAM(check_mem, "check memory"),
523    INIT_PARAM(memory_size, "memory size"),
524    INIT_PARAM(percent_reads, "target read percentage"),
525    INIT_PARAM(percent_functional, "percentage of access that are functional"),
526    INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
527    INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
528    INIT_PARAM(percent_source_unaligned,
529               "percent of copy source address that are unaligned"),
530    INIT_PARAM(percent_dest_unaligned,
531               "percent of copy dest address that are unaligned"),
532    INIT_PARAM(trace_addr, "address to trace"),
533                              INIT_PARAM(max_loads, "terminate when we have reached this load count"),
534    INIT_PARAM(atomic, "Is the tester testing atomic mode (or timing)")
535
536END_INIT_SIM_OBJECT_PARAMS(MemTest)
537
538
539CREATE_SIM_OBJECT(MemTest)
540{
541    return new MemTest(getInstanceName(), /*cache->getInterface(),*/ /*main_mem,*/
542                       /*check_mem,*/ memory_size, percent_reads, percent_functional,
543                       percent_uncacheable, progress_interval,
544                       percent_source_unaligned, percent_dest_unaligned,
545                       trace_addr, max_loads, atomic);
546}
547
548REGISTER_SIM_OBJECT("MemTest", MemTest)
549