SeriesRequestGenerator.cc revision 8975
16145SN/A/* 26386SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 37553SN/A * Copyright (c) 2009-2010 Advanced Micro Devices, Inc. 46386SN/A * All rights reserved. 56386SN/A * 66386SN/A * Redistribution and use in source and binary forms, with or without 76386SN/A * modification, are permitted provided that the following conditions are 86386SN/A * met: redistributions of source code must retain the above copyright 96386SN/A * notice, this list of conditions and the following disclaimer; 106386SN/A * redistributions in binary form must reproduce the above copyright 116386SN/A * notice, this list of conditions and the following disclaimer in the 126386SN/A * documentation and/or other materials provided with the distribution; 136386SN/A * neither the name of the copyright holders nor the names of its 146386SN/A * contributors may be used to endorse or promote products derived from 156386SN/A * this software without specific prior written permission. 166386SN/A * 176386SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186386SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196386SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206386SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216386SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226386SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236386SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246386SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256386SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266386SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276386SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286386SN/A */ 296145SN/A 307632SBrad.Beckmann@amd.com#include "cpu/testers/directedtest/DirectedGenerator.hh" 317632SBrad.Beckmann@amd.com#include "cpu/testers/directedtest/RubyDirectedTester.hh" 327632SBrad.Beckmann@amd.com#include "cpu/testers/directedtest/SeriesRequestGenerator.hh" 338232Snate@binkert.org#include "debug/DirectedTest.hh" 346145SN/A 357553SN/ASeriesRequestGenerator::SeriesRequestGenerator(const Params *p) 367553SN/A : DirectedGenerator(p) 376145SN/A{ 387553SN/A m_status = SeriesRequestGeneratorStatus_Thinking; 397553SN/A m_active_node = 0; 407553SN/A m_address = 0x0; 417553SN/A m_addr_increment_size = p->addr_increment_size; 427553SN/A m_issue_writes = p->issue_writes; 436145SN/A} 446145SN/A 457553SN/ASeriesRequestGenerator::~SeriesRequestGenerator() 466145SN/A{ 476145SN/A} 486145SN/A 497553SN/Abool 507553SN/ASeriesRequestGenerator::initiate() 516145SN/A{ 527553SN/A DPRINTF(DirectedTest, "initiating request\n"); 537553SN/A assert(m_status == SeriesRequestGeneratorStatus_Thinking); 546145SN/A 558950Sandreas.hansson@arm.com MasterPort* port = m_directed_tester->getCpuPort(m_active_node); 567553SN/A 577553SN/A Request::Flags flags; 587553SN/A 597553SN/A // For simplicity, requests are assumed to be 1 byte-sized 608832SAli.Saidi@ARM.com Request *req = new Request(m_address, 1, flags, masterId); 617553SN/A 627553SN/A Packet::Command cmd; 637553SN/A if (m_issue_writes) { 647553SN/A cmd = MemCmd::WriteReq; 657553SN/A } else { 667553SN/A cmd = MemCmd::ReadReq; 676145SN/A } 688949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, cmd); 697553SN/A uint8_t* dummyData = new uint8_t; 707553SN/A *dummyData = 0; 717553SN/A pkt->dataDynamic(dummyData); 726145SN/A 738975Sandreas.hansson@arm.com if (port->sendTimingReq(pkt)) { 747553SN/A DPRINTF(DirectedTest, "initiating request - successful\n"); 757553SN/A m_status = SeriesRequestGeneratorStatus_Request_Pending; 767553SN/A return true; 777553SN/A } else { 787553SN/A // If the packet did not issue, must delete 797553SN/A // Note: No need to delete the data, the packet destructor 807553SN/A // will delete it 817553SN/A delete pkt->req; 827553SN/A delete pkt; 837553SN/A 847553SN/A DPRINTF(DirectedTest, "failed to initiate request - sequencer not ready\n"); 857553SN/A return false; 867553SN/A } 876145SN/A} 886145SN/A 897553SN/Avoid 908655Sandreas.hansson@arm.comSeriesRequestGenerator::performCallback(uint32_t proc, Addr address) 916145SN/A{ 927553SN/A assert(m_active_node == proc); 937553SN/A assert(m_address == address); 947553SN/A assert(m_status == SeriesRequestGeneratorStatus_Request_Pending); 956145SN/A 967553SN/A m_status = SeriesRequestGeneratorStatus_Thinking; 977553SN/A m_active_node++; 987553SN/A if (m_active_node == m_num_cpus) { 997553SN/A // 1007553SN/A // Cycle of requests completed, increment cycle completions and restart 1017553SN/A // at cpu zero 1027553SN/A // 1037553SN/A m_directed_tester->incrementCycleCompletions(); 1047553SN/A m_address += m_addr_increment_size; 1057553SN/A m_active_node = 0; 1067553SN/A } 1076145SN/A} 1086145SN/A 1097553SN/ASeriesRequestGenerator * 1107553SN/ASeriesRequestGeneratorParams::create() 1116145SN/A{ 1127553SN/A return new SeriesRequestGenerator(this); 1136145SN/A} 114