InvalidateGenerator.cc revision 8975:7f36d4436074 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#include "cpu/testers/directedtest/DirectedGenerator.hh"
31#include "cpu/testers/directedtest/InvalidateGenerator.hh"
32#include "cpu/testers/directedtest/RubyDirectedTester.hh"
33#include "debug/DirectedTest.hh"
34
35InvalidateGenerator::InvalidateGenerator(const Params *p)
36    : DirectedGenerator(p)
37{
38    //
39    // First, issue loads to bring the block into S state
40    //
41    m_status = InvalidateGeneratorStatus_Load_Waiting;
42    m_active_read_node = 0;
43    m_active_inv_node = 0;
44    m_address = 0x0;
45    m_addr_increment_size = p->addr_increment_size;
46}
47
48InvalidateGenerator::~InvalidateGenerator()
49{
50}
51
52bool
53InvalidateGenerator::initiate()
54{
55    MasterPort* port;
56    Request::Flags flags;
57    PacketPtr pkt;
58    Packet::Command cmd;
59
60    // For simplicity, requests are assumed to be 1 byte-sized
61    Request *req = new Request(m_address, 1, flags, masterId);
62
63    //
64    // Based on the current state, issue a load or a store
65    //
66    if (m_status == InvalidateGeneratorStatus_Load_Waiting) {
67        DPRINTF(DirectedTest, "initiating read\n");
68        cmd = MemCmd::ReadReq;
69        port = m_directed_tester->getCpuPort(m_active_read_node);
70        pkt = new Packet(req, cmd);
71    } else if (m_status == InvalidateGeneratorStatus_Inv_Waiting) {
72        DPRINTF(DirectedTest, "initiating invalidating write\n");
73        cmd = MemCmd::WriteReq;
74        port = m_directed_tester->getCpuPort(m_active_inv_node);
75        pkt = new Packet(req, cmd);
76    } else {
77        panic("initiate was unexpectedly called\n");
78    }
79    uint8_t* dummyData = new uint8_t;
80    *dummyData = 0;
81    pkt->dataDynamic(dummyData);
82
83    if (port->sendTimingReq(pkt)) {
84        DPRINTF(DirectedTest, "initiating request - successful\n");
85        if (m_status == InvalidateGeneratorStatus_Load_Waiting) {
86            m_status = InvalidateGeneratorStatus_Load_Pending;
87        } else {
88            m_status = InvalidateGeneratorStatus_Inv_Pending;
89        }
90        return true;
91    } else {
92        // If the packet did not issue, must delete
93        // Note: No need to delete the data, the packet destructor
94        // will delete it
95        delete pkt->req;
96        delete pkt;
97
98        DPRINTF(DirectedTest, "failed to issue request - sequencer not ready\n");
99        return false;
100    }
101}
102
103void
104InvalidateGenerator::performCallback(uint32_t proc, Addr address)
105{
106    assert(m_address == address);
107
108    if (m_status == InvalidateGeneratorStatus_Load_Pending) {
109        assert(m_active_read_node == proc);
110        m_active_read_node++;
111        //
112        // Once all cpus have the block in S state, issue the invalidate
113        //
114        if (m_active_read_node == m_num_cpus) {
115            m_status = InvalidateGeneratorStatus_Inv_Waiting;
116            m_active_read_node = 0;
117        } else {
118            m_status = InvalidateGeneratorStatus_Load_Waiting;
119        }
120    } else if (m_status == InvalidateGeneratorStatus_Inv_Pending) {
121        assert(m_active_inv_node == proc);
122        m_active_inv_node++;
123        if (m_active_inv_node == m_num_cpus) {
124            m_address += m_addr_increment_size;
125            m_active_inv_node = 0;
126        }
127        //
128        // Invalidate completed, send that info to the tester and restart
129        // the cycle
130        //
131        m_directed_tester->incrementCycleCompletions();
132        m_status = InvalidateGeneratorStatus_Load_Waiting;
133    }
134
135}
136
137InvalidateGenerator *
138InvalidateGeneratorParams::create()
139{
140    return new InvalidateGenerator(this);
141}
142