InvalidateGenerator.cc revision 8655:e4001326a5ba 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#include "cpu/testers/directedtest/DirectedGenerator.hh"
31#include "cpu/testers/directedtest/InvalidateGenerator.hh"
32#include "cpu/testers/directedtest/RubyDirectedTester.hh"
33#include "debug/DirectedTest.hh"
34
35InvalidateGenerator::InvalidateGenerator(const Params *p)
36    : DirectedGenerator(p)
37{
38    //
39    // First, issue loads to bring the block into S state
40    //
41    m_status = InvalidateGeneratorStatus_Load_Waiting;
42    m_active_read_node = 0;
43    m_active_inv_node = 0;
44    m_address = 0x0;
45    m_addr_increment_size = p->addr_increment_size;
46}
47
48InvalidateGenerator::~InvalidateGenerator()
49{
50}
51
52bool
53InvalidateGenerator::initiate()
54{
55    RubyDirectedTester::CpuPort* port;
56    Request::Flags flags;
57    PacketPtr pkt;
58    Packet::Command cmd;
59
60    // For simplicity, requests are assumed to be 1 byte-sized
61    Request *req = new Request(m_address, 1, flags);
62
63    //
64    // Based on the current state, issue a load or a store
65    //
66    if (m_status == InvalidateGeneratorStatus_Load_Waiting) {
67        DPRINTF(DirectedTest, "initiating read\n");
68        cmd = MemCmd::ReadReq;
69        port = safe_cast<RubyDirectedTester::CpuPort*>(m_directed_tester->
70                                               getCpuPort(m_active_read_node));
71        pkt = new Packet(req, cmd, m_active_read_node);
72    } else if (m_status == InvalidateGeneratorStatus_Inv_Waiting) {
73        DPRINTF(DirectedTest, "initiating invalidating write\n");
74        cmd = MemCmd::WriteReq;
75        port = safe_cast<RubyDirectedTester::CpuPort*>(m_directed_tester->
76                                               getCpuPort(m_active_inv_node));
77        pkt = new Packet(req, cmd, m_active_inv_node);
78    } else {
79        panic("initiate was unexpectedly called\n");
80    }
81    uint8_t* dummyData = new uint8_t;
82    *dummyData = 0;
83    pkt->dataDynamic(dummyData);
84
85    if (port->sendTiming(pkt)) {
86        DPRINTF(DirectedTest, "initiating request - successful\n");
87        if (m_status == InvalidateGeneratorStatus_Load_Waiting) {
88            m_status = InvalidateGeneratorStatus_Load_Pending;
89        } else {
90            m_status = InvalidateGeneratorStatus_Inv_Pending;
91        }
92        return true;
93    } else {
94        // If the packet did not issue, must delete
95        // Note: No need to delete the data, the packet destructor
96        // will delete it
97        delete pkt->req;
98        delete pkt;
99
100        DPRINTF(DirectedTest, "failed to issue request - sequencer not ready\n");
101        return false;
102    }
103}
104
105void
106InvalidateGenerator::performCallback(uint32_t proc, Addr address)
107{
108    assert(m_address == address);
109
110    if (m_status == InvalidateGeneratorStatus_Load_Pending) {
111        assert(m_active_read_node == proc);
112        m_active_read_node++;
113        //
114        // Once all cpus have the block in S state, issue the invalidate
115        //
116        if (m_active_read_node == m_num_cpus) {
117            m_status = InvalidateGeneratorStatus_Inv_Waiting;
118            m_active_read_node = 0;
119        } else {
120            m_status = InvalidateGeneratorStatus_Load_Waiting;
121        }
122    } else if (m_status == InvalidateGeneratorStatus_Inv_Pending) {
123        assert(m_active_inv_node == proc);
124        m_active_inv_node++;
125        if (m_active_inv_node == m_num_cpus) {
126            m_address += m_addr_increment_size;
127            m_active_inv_node = 0;
128        }
129        //
130        // Invalidate completed, send that info to the tester and restart
131        // the cycle
132        //
133        m_directed_tester->incrementCycleCompletions();
134        m_status = InvalidateGeneratorStatus_Load_Waiting;
135    }
136
137}
138
139InvalidateGenerator *
140InvalidateGeneratorParams::create()
141{
142    return new InvalidateGenerator(this);
143}
144