InvalidateGenerator.cc revision 8229:78bf55f23338
1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#include "cpu/testers/directedtest/DirectedGenerator.hh" 31#include "cpu/testers/directedtest/InvalidateGenerator.hh" 32#include "cpu/testers/directedtest/RubyDirectedTester.hh" 33 34InvalidateGenerator::InvalidateGenerator(const Params *p) 35 : DirectedGenerator(p) 36{ 37 // 38 // First, issue loads to bring the block into S state 39 // 40 m_status = InvalidateGeneratorStatus_Load_Waiting; 41 m_active_read_node = 0; 42 m_active_inv_node = 0; 43 m_address = 0x0; 44 m_addr_increment_size = p->addr_increment_size; 45} 46 47InvalidateGenerator::~InvalidateGenerator() 48{ 49} 50 51bool 52InvalidateGenerator::initiate() 53{ 54 RubyDirectedTester::CpuPort* port; 55 Request::Flags flags; 56 PacketPtr pkt; 57 Packet::Command cmd; 58 59 // For simplicity, requests are assumed to be 1 byte-sized 60 Request *req = new Request(m_address, 1, flags); 61 62 // 63 // Based on the current state, issue a load or a store 64 // 65 if (m_status == InvalidateGeneratorStatus_Load_Waiting) { 66 DPRINTF(DirectedTest, "initiating read\n"); 67 cmd = MemCmd::ReadReq; 68 port = safe_cast<RubyDirectedTester::CpuPort*>(m_directed_tester-> 69 getCpuPort(m_active_read_node)); 70 pkt = new Packet(req, cmd, m_active_read_node); 71 } else if (m_status == InvalidateGeneratorStatus_Inv_Waiting) { 72 DPRINTF(DirectedTest, "initiating invalidating write\n"); 73 cmd = MemCmd::WriteReq; 74 port = safe_cast<RubyDirectedTester::CpuPort*>(m_directed_tester-> 75 getCpuPort(m_active_inv_node)); 76 pkt = new Packet(req, cmd, m_active_inv_node); 77 } else { 78 panic("initiate was unexpectedly called\n"); 79 } 80 uint8_t* dummyData = new uint8_t; 81 *dummyData = 0; 82 pkt->dataDynamic(dummyData); 83 84 if (port->sendTiming(pkt)) { 85 DPRINTF(DirectedTest, "initiating request - successful\n"); 86 if (m_status == InvalidateGeneratorStatus_Load_Waiting) { 87 m_status = InvalidateGeneratorStatus_Load_Pending; 88 } else { 89 m_status = InvalidateGeneratorStatus_Inv_Pending; 90 } 91 return true; 92 } else { 93 // If the packet did not issue, must delete 94 // Note: No need to delete the data, the packet destructor 95 // will delete it 96 delete pkt->req; 97 delete pkt; 98 99 DPRINTF(DirectedTest, "failed to issue request - sequencer not ready\n"); 100 return false; 101 } 102} 103 104void 105InvalidateGenerator::performCallback(uint proc, Addr address) 106{ 107 assert(m_address == address); 108 109 if (m_status == InvalidateGeneratorStatus_Load_Pending) { 110 assert(m_active_read_node == proc); 111 m_active_read_node++; 112 // 113 // Once all cpus have the block in S state, issue the invalidate 114 // 115 if (m_active_read_node == m_num_cpus) { 116 m_status = InvalidateGeneratorStatus_Inv_Waiting; 117 m_active_read_node = 0; 118 } else { 119 m_status = InvalidateGeneratorStatus_Load_Waiting; 120 } 121 } else if (m_status == InvalidateGeneratorStatus_Inv_Pending) { 122 assert(m_active_inv_node == proc); 123 m_active_inv_node++; 124 if (m_active_inv_node == m_num_cpus) { 125 m_address += m_addr_increment_size; 126 m_active_inv_node = 0; 127 } 128 // 129 // Invalidate completed, send that info to the tester and restart 130 // the cycle 131 // 132 m_directed_tester->incrementCycleCompletions(); 133 m_status = InvalidateGeneratorStatus_Load_Waiting; 134 } 135 136} 137 138InvalidateGenerator * 139InvalidateGeneratorParams::create() 140{ 141 return new InvalidateGenerator(this); 142} 143