InvalidateGenerator.cc revision 11793:ef606668d247 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#include "cpu/testers/directedtest/InvalidateGenerator.hh"
31
32#include "cpu/testers/directedtest/DirectedGenerator.hh"
33#include "cpu/testers/directedtest/RubyDirectedTester.hh"
34#include "debug/DirectedTest.hh"
35
36InvalidateGenerator::InvalidateGenerator(const Params *p)
37    : DirectedGenerator(p)
38{
39    //
40    // First, issue loads to bring the block into S state
41    //
42    m_status = InvalidateGeneratorStatus_Load_Waiting;
43    m_active_read_node = 0;
44    m_active_inv_node = 0;
45    m_address = 0x0;
46    m_addr_increment_size = p->addr_increment_size;
47}
48
49InvalidateGenerator::~InvalidateGenerator()
50{
51}
52
53bool
54InvalidateGenerator::initiate()
55{
56    MasterPort* port;
57    Request::Flags flags;
58    PacketPtr pkt;
59    Packet::Command cmd;
60
61    // For simplicity, requests are assumed to be 1 byte-sized
62    Request *req = new Request(m_address, 1, flags, masterId);
63
64    //
65    // Based on the current state, issue a load or a store
66    //
67    if (m_status == InvalidateGeneratorStatus_Load_Waiting) {
68        DPRINTF(DirectedTest, "initiating read\n");
69        cmd = MemCmd::ReadReq;
70        port = m_directed_tester->getCpuPort(m_active_read_node);
71        pkt = new Packet(req, cmd);
72    } else if (m_status == InvalidateGeneratorStatus_Inv_Waiting) {
73        DPRINTF(DirectedTest, "initiating invalidating write\n");
74        cmd = MemCmd::WriteReq;
75        port = m_directed_tester->getCpuPort(m_active_inv_node);
76        pkt = new Packet(req, cmd);
77    } else {
78        panic("initiate was unexpectedly called\n");
79    }
80    pkt->allocate();
81
82    if (port->sendTimingReq(pkt)) {
83        DPRINTF(DirectedTest, "initiating request - successful\n");
84        if (m_status == InvalidateGeneratorStatus_Load_Waiting) {
85            m_status = InvalidateGeneratorStatus_Load_Pending;
86        } else {
87            m_status = InvalidateGeneratorStatus_Inv_Pending;
88        }
89        return true;
90    } else {
91        // If the packet did not issue, must delete
92        // Note: No need to delete the data, the packet destructor
93        // will delete it
94        delete pkt->req;
95        delete pkt;
96
97        DPRINTF(DirectedTest, "failed to issue request - sequencer not ready\n");
98        return false;
99    }
100}
101
102void
103InvalidateGenerator::performCallback(uint32_t proc, Addr address)
104{
105    assert(m_address == address);
106
107    if (m_status == InvalidateGeneratorStatus_Load_Pending) {
108        assert(m_active_read_node == proc);
109        m_active_read_node++;
110        //
111        // Once all cpus have the block in S state, issue the invalidate
112        //
113        if (m_active_read_node == m_num_cpus) {
114            m_status = InvalidateGeneratorStatus_Inv_Waiting;
115            m_active_read_node = 0;
116        } else {
117            m_status = InvalidateGeneratorStatus_Load_Waiting;
118        }
119    } else if (m_status == InvalidateGeneratorStatus_Inv_Pending) {
120        assert(m_active_inv_node == proc);
121        m_active_inv_node++;
122        if (m_active_inv_node == m_num_cpus) {
123            m_address += m_addr_increment_size;
124            m_active_inv_node = 0;
125        }
126        //
127        // Invalidate completed, send that info to the tester and restart
128        // the cycle
129        //
130        m_directed_tester->incrementCycleCompletions();
131        m_status = InvalidateGeneratorStatus_Load_Waiting;
132    }
133
134}
135
136InvalidateGenerator *
137InvalidateGeneratorParams::create()
138{
139    return new InvalidateGenerator(this);
140}
141