static_inst.hh revision 8902:75b524b64c28
12SN/A/* 211071SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 311071SN/A * All rights reserved. 411071SN/A * 511071SN/A * Redistribution and use in source and binary forms, with or without 611071SN/A * modification, are permitted provided that the following conditions are 711071SN/A * met: redistributions of source code must retain the above copyright 811071SN/A * notice, this list of conditions and the following disclaimer; 911071SN/A * redistributions in binary form must reproduce the above copyright 1011071SN/A * notice, this list of conditions and the following disclaimer in the 1111071SN/A * documentation and/or other materials provided with the distribution; 1211071SN/A * neither the name of the copyright holders nor the names of its 1311071SN/A * contributors may be used to endorse or promote products derived from 141762SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A * 282SN/A * Authors: Steve Reinhardt 292SN/A */ 302SN/A 312SN/A#ifndef __CPU_STATIC_INST_HH__ 322SN/A#define __CPU_STATIC_INST_HH__ 332SN/A 342SN/A#include <bitset> 352SN/A#include <string> 362SN/A 372SN/A#include "arch/registers.hh" 382SN/A#include "arch/types.hh" 392665SN/A#include "base/misc.hh" 402665SN/A#include "base/refcnt.hh" 412665SN/A#include "base/types.hh" 422SN/A#include "config/the_isa.hh" 432SN/A#include "cpu/op_class.hh" 442SN/A#include "cpu/static_inst_fwd.hh" 452SN/A#include "sim/fault_fwd.hh" 462SN/A 472SN/A// forward declarations 4811263Sandreas.sandberg@arm.comstruct AlphaSimpleImpl; 4911263Sandreas.sandberg@arm.comstruct OzoneImpl; 50146SN/Astruct SimpleImpl; 512SN/Aclass ThreadContext; 522SN/Aclass DynInst; 532SN/Aclass Packet; 542SN/A 551954SN/Astruct O3CPUImpl; 56146SN/Atemplate <class Impl> class BaseO3DynInst; 578232SN/Atypedef BaseO3DynInst<O3CPUImpl> O3DynInst; 588232SN/Atemplate <class Impl> class OzoneDynInst; 5911263Sandreas.sandberg@arm.comclass InOrderDynInst; 6011263Sandreas.sandberg@arm.com 6111263Sandreas.sandberg@arm.comclass CheckerCPU; 624762SN/Aclass FastCPU; 638229SN/Aclass AtomicSimpleCPU; 641078SN/Aclass TimingSimpleCPU; 651078SN/Aclass InorderCPU; 662SN/Aclass SymbolTable; 672SN/A 682SN/Anamespace Trace { 694981SN/A class InstRecord; 7013766Sgabeblack@google.com} 712SN/A 725034SN/A/** 735034SN/A * Base, ISA-independent static instruction class. 745034SN/A * 755034SN/A * The main component of this class is the vector of flags and the 762SN/A * associated methods for reading them. Any object that can rely 774981SN/A * solely on these flags can process instructions without being 784981SN/A * recompiled for multiple ISAs. 794981SN/A */ 802SN/Aclass StaticInst : public RefCounted 812SN/A{ 822SN/A public: 832SN/A /// Binary extended machine instruction type. 841435SN/A typedef TheISA::ExtMachInst ExtMachInst; 851435SN/A /// Logical register index type. 862SN/A typedef TheISA::RegIndex RegIndex; 871435SN/A 881435SN/A enum { 892SN/A MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 902SN/A MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 9113784Sgabeblack@google.com }; 9213784Sgabeblack@google.com 934981SN/A /// Set of boolean static instruction properties. 944981SN/A /// 9513784Sgabeblack@google.com /// Notes: 964981SN/A /// - The IsInteger and IsFloating flags are based on the class of 9713784Sgabeblack@google.com /// registers accessed by the instruction. Although most 9813784Sgabeblack@google.com /// instructions will have exactly one of these two flags set, it 994981SN/A /// is possible for an instruction to have neither (e.g., direct 1004981SN/A /// unconditional branches, memory barriers) or both (e.g., an 1014981SN/A /// FP/int conversion). 102633SN/A /// - If IsMemRef is set, then exactly one of IsLoad or IsStore 1032SN/A /// will be set. 1042SN/A /// - If IsControl is set, then exactly one of IsDirectControl or 1052SN/A /// IsIndirect Control will be set, and exactly one of 1062SN/A /// IsCondControl or IsUncondControl will be set. 1072SN/A /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are 1082SN/A /// implemented as flags since in the current model there's no 1091435SN/A /// other way for instructions to inject behavior into the 1101954SN/A /// pipeline outside of fetch. Once we go to an exec-in-exec CPU 1111435SN/A /// model we should be able to get rid of these flags and 1121954SN/A /// implement this behavior via the execute() methods. 11312087Sspwilson2@wisc.edu /// 11412087Sspwilson2@wisc.edu enum Flags { 1151435SN/A IsNop, ///< Is a no-op (no effect at all). 1162SN/A 1172SN/A IsInteger, ///< References integer regs. 11810905SN/A IsFloating, ///< References FP regs. 119558SN/A 12010905SN/A IsMemRef, ///< References memory (load, store, or prefetch). 12110905SN/A IsLoad, ///< Reads from memory (load or prefetch). 122558SN/A IsStore, ///< Writes to memory. 123558SN/A IsStoreConditional, ///< Store conditional instruction. 124558SN/A IsIndexed, ///< Accesses memory with an indexed address computation 12510905SN/A IsInstPrefetch, ///< Instruction-cache prefetch. 126558SN/A IsDataPrefetch, ///< Data-cache prefetch. 12710905SN/A 12810905SN/A IsControl, ///< Control transfer instruction. 129558SN/A IsDirectControl, ///< PC relative control transfer. 130558SN/A IsIndirectControl, ///< Register indirect control transfer. 131558SN/A IsCondControl, ///< Conditional control transfer. 1322566SN/A IsUncondControl, ///< Unconditional control transfer. 133633SN/A IsCall, ///< Subroutine call. 134633SN/A IsReturn, ///< Subroutine return. 135633SN/A 136633SN/A IsCondDelaySlot,///< Conditional Delay-Slot Instruction 137633SN/A 138633SN/A IsThreadSync, ///< Thread synchronization operation. 139633SN/A 1402SN/A IsSerializing, ///< Serializes pipeline: won't execute until all 1412SN/A /// older instructions have committed. 1422SN/A IsSerializeBefore, 1432SN/A IsSerializeAfter, 1442SN/A IsMemBarrier, ///< Is a memory barrier 145633SN/A IsWriteBarrier, ///< Is a write barrier 146633SN/A IsReadBarrier, ///< Is a read barrier 14711071SN/A IsERET, /// <- Causes the IFU to stall (MIPS ISA) 14811071SN/A 14911071SN/A IsNonSpeculative, ///< Should not be executed speculatively 150633SN/A IsQuiesce, ///< Is a quiesce instruction 15111071SN/A 152633SN/A IsIprAccess, ///< Accesses IPRs 153633SN/A IsUnverifiable, ///< Can't be verified by a checker 154195SN/A 1552SN/A IsSyscall, ///< Causes a system call to be emulated in syscall 1562SN/A /// emulation mode. 1572SN/A 1582SN/A //Flags for microcode 1592SN/A IsMacroop, ///< Is a macroop containing microops 1602SN/A IsMicroop, ///< Is a microop 16111071SN/A IsDelayedCommit, ///< This microop doesn't commit right away 16211071SN/A IsLastMicroop, ///< This microop ends a microop sequence 16311071SN/A IsFirstMicroop, ///< This microop begins a microop sequence 16411071SN/A //This flag doesn't do anything yet 16511071SN/A IsMicroBranch, ///< This microop branches within the microcode for a macroop 16611071SN/A IsDspOp, 16711071SN/A IsSquashAfter, ///< Squash all uncommitted state after executed 16811071SN/A NumFlags 16911071SN/A }; 17011071SN/A 17111071SN/A protected: 17211071SN/A 17311071SN/A /// Flag values for this instruction. 17411071SN/A std::bitset<NumFlags> flags; 17511071SN/A 17611071SN/A /// See opClass(). 17711071SN/A OpClass _opClass; 1782SN/A 1792566SN/A /// See numSrcRegs(). 1802SN/A int8_t _numSrcRegs; 1812SN/A 182633SN/A /// See numDestRegs(). 1832SN/A int8_t _numDestRegs; 1842SN/A 1852SN/A /// The following are used to track physical register usage 186633SN/A /// for machines with separate int & FP reg files. 1872SN/A //@{ 1882SN/A int8_t _numFPDestRegs; 1892SN/A int8_t _numIntDestRegs; 19011701Smichael.lebeane@amd.com //@} 1915190SN/A 1925190SN/A public: 1935190SN/A 194633SN/A /// @name Register information. 195633SN/A /// The sum of numFPDestRegs() and numIntDestRegs() equals 1967823SN/A /// numDestRegs(). The former two functions are used to track 1972SN/A /// physical register usage for machines with separate int & FP 1982SN/A /// reg files. 1992SN/A //@{ 2002SN/A /// Number of source registers. 201558SN/A int8_t numSrcRegs() const { return _numSrcRegs; } 20210905SN/A /// Number of destination registers. 203558SN/A int8_t numDestRegs() const { return _numDestRegs; } 20410469SN/A /// Number of floating-point destination regs. 20510905SN/A int8_t numFPDestRegs() const { return _numFPDestRegs; } 2061435SN/A /// Number of integer destination regs. 20710905SN/A int8_t numIntDestRegs() const { return _numIntDestRegs; } 208558SN/A //@} 209633SN/A 21010905SN/A /// @name Flag accessors. 211558SN/A /// These functions are used to access the values of the various 212633SN/A /// instruction property flags. See StaticInst::Flags for descriptions 21310905SN/A /// of the individual flags. 214574SN/A //@{ 215574SN/A 21611071SN/A bool isNop() const { return flags[IsNop]; } 21711071SN/A 21811071SN/A bool isMemRef() const { return flags[IsMemRef]; } 21911071SN/A bool isLoad() const { return flags[IsLoad]; } 22011071SN/A bool isStore() const { return flags[IsStore]; } 22111071SN/A bool isStoreConditional() const { return flags[IsStoreConditional]; } 22211071SN/A bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 22311071SN/A bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 22411071SN/A bool isPrefetch() const { return isInstPrefetch() || 225558SN/A isDataPrefetch(); } 226558SN/A 227558SN/A bool isInteger() const { return flags[IsInteger]; } 22810905SN/A bool isFloating() const { return flags[IsFloating]; } 229558SN/A 230574SN/A bool isControl() const { return flags[IsControl]; } 23110905SN/A bool isCall() const { return flags[IsCall]; } 232574SN/A bool isReturn() const { return flags[IsReturn]; } 23311701Smichael.lebeane@amd.com bool isDirectCtrl() const { return flags[IsDirectControl]; } 23410905SN/A bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 235558SN/A bool isCondCtrl() const { return flags[IsCondControl]; } 236558SN/A bool isUncondCtrl() const { return flags[IsUncondControl]; } 237574SN/A bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; } 23810905SN/A 239558SN/A bool isThreadSync() const { return flags[IsThreadSync]; } 240574SN/A bool isSerializing() const { return flags[IsSerializing] || 24110905SN/A flags[IsSerializeBefore] || 2425606SN/A flags[IsSerializeAfter]; } 243558SN/A bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 24411071SN/A bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 24511071SN/A bool isSquashAfter() const { return flags[IsSquashAfter]; } 24611071SN/A bool isMemBarrier() const { return flags[IsMemBarrier]; } 24711071SN/A bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 24811071SN/A bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 24911701Smichael.lebeane@amd.com bool isQuiesce() const { return flags[IsQuiesce]; } 25011071SN/A bool isIprAccess() const { return flags[IsIprAccess]; } 25111071SN/A bool isUnverifiable() const { return flags[IsUnverifiable]; } 25211071SN/A bool isSyscall() const { return flags[IsSyscall]; } 25311071SN/A bool isMacroop() const { return flags[IsMacroop]; } 25411071SN/A bool isMicroop() const { return flags[IsMicroop]; } 25511071SN/A bool isDelayedCommit() const { return flags[IsDelayedCommit]; } 25611071SN/A bool isLastMicroop() const { return flags[IsLastMicroop]; } 25711071SN/A bool isFirstMicroop() const { return flags[IsFirstMicroop]; } 25811071SN/A //This flag doesn't do anything yet 25911071SN/A bool isMicroBranch() const { return flags[IsMicroBranch]; } 26011071SN/A //@} 26111071SN/A 26211071SN/A void setLastMicroop() { flags[IsLastMicroop] = true; } 26311071SN/A void setDelayedCommit() { flags[IsDelayedCommit] = true; } 26411071SN/A void setFlag(Flags f) { flags[f] = true; } 26511071SN/A 26611071SN/A /// Operation class. Used to select appropriate function unit in issue. 26711071SN/A OpClass opClass() const { return _opClass; } 26811071SN/A 269558SN/A 270558SN/A /// Return logical index (architectural reg num) of i'th destination reg. 2714762SN/A /// Only the entries from 0 through numDestRegs()-1 are valid. 2724762SN/A RegIndex destRegIdx(int i) const { return _destRegIdx[i]; } 2732SN/A 2744981SN/A /// Return logical index (architectural reg num) of i'th source reg. 2752SN/A /// Only the entries from 0 through numSrcRegs()-1 are valid. 276 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; } 277 278 /// Pointer to a statically allocated "null" instruction object. 279 /// Used to give eaCompInst() and memAccInst() something to return 280 /// when called on non-memory instructions. 281 static StaticInstPtr nullStaticInstPtr; 282 283 /** 284 * Memory references only: returns "fake" instruction representing 285 * the effective address part of the memory operation. Used to 286 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 287 * just the EA computation. 288 */ 289 virtual const 290 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; } 291 292 /** 293 * Memory references only: returns "fake" instruction representing 294 * the memory access part of the memory operation. Used to 295 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 296 * just the memory access (not the EA computation). 297 */ 298 virtual const 299 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; } 300 301 /// The binary machine instruction. 302 const ExtMachInst machInst; 303 304 protected: 305 306 /// See destRegIdx(). 307 RegIndex _destRegIdx[MaxInstDestRegs]; 308 /// See srcRegIdx(). 309 RegIndex _srcRegIdx[MaxInstSrcRegs]; 310 311 /** 312 * Base mnemonic (e.g., "add"). Used by generateDisassembly() 313 * methods. Also useful to readily identify instructions from 314 * within the debugger when #cachedDisassembly has not been 315 * initialized. 316 */ 317 const char *mnemonic; 318 319 /** 320 * String representation of disassembly (lazily evaluated via 321 * disassemble()). 322 */ 323 mutable std::string *cachedDisassembly; 324 325 /** 326 * Internal function to generate disassembly string. 327 */ 328 virtual std::string 329 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 330 331 /// Constructor. 332 /// It's important to initialize everything here to a sane 333 /// default, since the decoder generally only overrides 334 /// the fields that are meaningful for the particular 335 /// instruction. 336 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) 337 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 338 _numFPDestRegs(0), _numIntDestRegs(0), 339 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) 340 { } 341 342 public: 343 virtual ~StaticInst(); 344 345/** 346 * The execute() signatures are auto-generated by scons based on the 347 * set of CPU models we are compiling in today. 348 */ 349#include "cpu/static_inst_exec_sigs.hh" 350 351 virtual void advancePC(TheISA::PCState &pcState) const = 0; 352 353 /** 354 * Return the microop that goes with a particular micropc. This should 355 * only be defined/used in macroops which will contain microops 356 */ 357 virtual StaticInstPtr fetchMicroop(MicroPC upc) const; 358 359 /** 360 * Return the target address for a PC-relative branch. 361 * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 362 * should be true). 363 */ 364 virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const; 365 366 /** 367 * Return the target address for an indirect branch (jump). The 368 * register value is read from the supplied thread context, so 369 * the result is valid only if the thread context is about to 370 * execute the branch in question. Invalid if not an indirect 371 * branch (i.e. isIndirectCtrl() should be true). 372 */ 373 virtual TheISA::PCState branchTarget(ThreadContext *tc) const; 374 375 /** 376 * Return true if the instruction is a control transfer, and if so, 377 * return the target address as well. 378 */ 379 bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, 380 TheISA::PCState &tgt) const; 381 382 /** 383 * Return string representation of disassembled instruction. 384 * The default version of this function will call the internal 385 * virtual generateDisassembly() function to get the string, 386 * then cache it in #cachedDisassembly. If the disassembly 387 * should not be cached, this function should be overridden directly. 388 */ 389 virtual const std::string &disassemble(Addr pc, 390 const SymbolTable *symtab = 0) const; 391 392 /// Return name of machine instruction 393 std::string getName() { return mnemonic; } 394}; 395 396#endif // __CPU_STATIC_INST_HH__ 397