static_inst.hh revision 8541:27aaee8ec7cc 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_STATIC_INST_HH__
32#define __CPU_STATIC_INST_HH__
33
34#include <bitset>
35#include <string>
36
37#include "arch/registers.hh"
38#include "arch/types.hh"
39#include "base/misc.hh"
40#include "base/refcnt.hh"
41#include "base/types.hh"
42#include "config/the_isa.hh"
43#include "cpu/op_class.hh"
44#include "sim/fault_fwd.hh"
45
46// forward declarations
47struct AlphaSimpleImpl;
48struct OzoneImpl;
49struct SimpleImpl;
50class ThreadContext;
51class DynInst;
52class Packet;
53
54class O3CPUImpl;
55template <class Impl> class BaseO3DynInst;
56typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
57template <class Impl> class OzoneDynInst;
58class InOrderDynInst;
59
60class CheckerCPU;
61class FastCPU;
62class AtomicSimpleCPU;
63class TimingSimpleCPU;
64class InorderCPU;
65class SymbolTable;
66
67namespace Trace {
68    class InstRecord;
69}
70
71/**
72 * Base, ISA-independent static instruction class.
73 *
74 * The main component of this class is the vector of flags and the
75 * associated methods for reading them.  Any object that can rely
76 * solely on these flags can process instructions without being
77 * recompiled for multiple ISAs.
78 */
79class StaticInstBase : public RefCounted
80{
81  public:
82
83    /// Set of boolean static instruction properties.
84    ///
85    /// Notes:
86    /// - The IsInteger and IsFloating flags are based on the class of
87    /// registers accessed by the instruction.  Although most
88    /// instructions will have exactly one of these two flags set, it
89    /// is possible for an instruction to have neither (e.g., direct
90    /// unconditional branches, memory barriers) or both (e.g., an
91    /// FP/int conversion).
92    /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
93    /// will be set.
94    /// - If IsControl is set, then exactly one of IsDirectControl or
95    /// IsIndirect Control will be set, and exactly one of
96    /// IsCondControl or IsUncondControl will be set.
97    /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
98    /// implemented as flags since in the current model there's no
99    /// other way for instructions to inject behavior into the
100    /// pipeline outside of fetch.  Once we go to an exec-in-exec CPU
101    /// model we should be able to get rid of these flags and
102    /// implement this behavior via the execute() methods.
103    ///
104    enum Flags {
105        IsNop,          ///< Is a no-op (no effect at all).
106
107        IsInteger,      ///< References integer regs.
108        IsFloating,     ///< References FP regs.
109
110        IsMemRef,       ///< References memory (load, store, or prefetch).
111        IsLoad,         ///< Reads from memory (load or prefetch).
112        IsStore,        ///< Writes to memory.
113        IsStoreConditional,    ///< Store conditional instruction.
114        IsIndexed,      ///< Accesses memory with an indexed address computation
115        IsInstPrefetch, ///< Instruction-cache prefetch.
116        IsDataPrefetch, ///< Data-cache prefetch.
117
118        IsControl,              ///< Control transfer instruction.
119        IsDirectControl,        ///< PC relative control transfer.
120        IsIndirectControl,      ///< Register indirect control transfer.
121        IsCondControl,          ///< Conditional control transfer.
122        IsUncondControl,        ///< Unconditional control transfer.
123        IsCall,                 ///< Subroutine call.
124        IsReturn,               ///< Subroutine return.
125
126        IsCondDelaySlot,///< Conditional Delay-Slot Instruction
127
128        IsThreadSync,   ///< Thread synchronization operation.
129
130        IsSerializing,  ///< Serializes pipeline: won't execute until all
131                        /// older instructions have committed.
132        IsSerializeBefore,
133        IsSerializeAfter,
134        IsMemBarrier,   ///< Is a memory barrier
135        IsWriteBarrier, ///< Is a write barrier
136        IsReadBarrier,  ///< Is a read barrier
137        IsERET, /// <- Causes the IFU to stall (MIPS ISA)
138
139        IsNonSpeculative, ///< Should not be executed speculatively
140        IsQuiesce,      ///< Is a quiesce instruction
141
142        IsIprAccess,    ///< Accesses IPRs
143        IsUnverifiable, ///< Can't be verified by a checker
144
145        IsSyscall,      ///< Causes a system call to be emulated in syscall
146                        /// emulation mode.
147
148        //Flags for microcode
149        IsMacroop,      ///< Is a macroop containing microops
150        IsMicroop,      ///< Is a microop
151        IsDelayedCommit,        ///< This microop doesn't commit right away
152        IsLastMicroop,  ///< This microop ends a microop sequence
153        IsFirstMicroop, ///< This microop begins a microop sequence
154        //This flag doesn't do anything yet
155        IsMicroBranch,  ///< This microop branches within the microcode for a macroop
156        IsDspOp,
157        IsSquashAfter, ///< Squash all uncommitted state after executed
158        NumFlags
159    };
160
161  protected:
162
163    /// Flag values for this instruction.
164    std::bitset<NumFlags> flags;
165
166    /// See opClass().
167    OpClass _opClass;
168
169    /// See numSrcRegs().
170    int8_t _numSrcRegs;
171
172    /// See numDestRegs().
173    int8_t _numDestRegs;
174
175    /// The following are used to track physical register usage
176    /// for machines with separate int & FP reg files.
177    //@{
178    int8_t _numFPDestRegs;
179    int8_t _numIntDestRegs;
180    //@}
181
182    /// Constructor.
183    /// It's important to initialize everything here to a sane
184    /// default, since the decoder generally only overrides
185    /// the fields that are meaningful for the particular
186    /// instruction.
187    StaticInstBase(OpClass __opClass)
188        : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
189          _numFPDestRegs(0), _numIntDestRegs(0)
190    {
191    }
192
193  public:
194
195    /// @name Register information.
196    /// The sum of numFPDestRegs() and numIntDestRegs() equals
197    /// numDestRegs().  The former two functions are used to track
198    /// physical register usage for machines with separate int & FP
199    /// reg files.
200    //@{
201    /// Number of source registers.
202    int8_t numSrcRegs()  const { return _numSrcRegs; }
203    /// Number of destination registers.
204    int8_t numDestRegs() const { return _numDestRegs; }
205    /// Number of floating-point destination regs.
206    int8_t numFPDestRegs()  const { return _numFPDestRegs; }
207    /// Number of integer destination regs.
208    int8_t numIntDestRegs() const { return _numIntDestRegs; }
209    //@}
210
211    /// @name Flag accessors.
212    /// These functions are used to access the values of the various
213    /// instruction property flags.  See StaticInstBase::Flags for descriptions
214    /// of the individual flags.
215    //@{
216
217    bool isNop()          const { return flags[IsNop]; }
218
219    bool isMemRef()       const { return flags[IsMemRef]; }
220    bool isLoad()         const { return flags[IsLoad]; }
221    bool isStore()        const { return flags[IsStore]; }
222    bool isStoreConditional()     const { return flags[IsStoreConditional]; }
223    bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
224    bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
225    bool isPrefetch()     const { return isInstPrefetch() ||
226                                         isDataPrefetch(); }
227
228    bool isInteger()      const { return flags[IsInteger]; }
229    bool isFloating()     const { return flags[IsFloating]; }
230
231    bool isControl()      const { return flags[IsControl]; }
232    bool isCall()         const { return flags[IsCall]; }
233    bool isReturn()       const { return flags[IsReturn]; }
234    bool isDirectCtrl()   const { return flags[IsDirectControl]; }
235    bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
236    bool isCondCtrl()     const { return flags[IsCondControl]; }
237    bool isUncondCtrl()   const { return flags[IsUncondControl]; }
238    bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
239
240    bool isThreadSync()   const { return flags[IsThreadSync]; }
241    bool isSerializing()  const { return flags[IsSerializing] ||
242                                      flags[IsSerializeBefore] ||
243                                      flags[IsSerializeAfter]; }
244    bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
245    bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
246    bool isSquashAfter() const { return flags[IsSquashAfter]; }
247    bool isMemBarrier()   const { return flags[IsMemBarrier]; }
248    bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
249    bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
250    bool isQuiesce() const { return flags[IsQuiesce]; }
251    bool isIprAccess() const { return flags[IsIprAccess]; }
252    bool isUnverifiable() const { return flags[IsUnverifiable]; }
253    bool isSyscall() const { return flags[IsSyscall]; }
254    bool isMacroop() const { return flags[IsMacroop]; }
255    bool isMicroop() const { return flags[IsMicroop]; }
256    bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
257    bool isLastMicroop() const { return flags[IsLastMicroop]; }
258    bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
259    //This flag doesn't do anything yet
260    bool isMicroBranch() const { return flags[IsMicroBranch]; }
261    //@}
262
263    void setLastMicroop() { flags[IsLastMicroop] = true; }
264    void setDelayedCommit() { flags[IsDelayedCommit] = true; }
265    void setFlag(Flags f) { flags[f] = true; }
266
267    /// Operation class.  Used to select appropriate function unit in issue.
268    OpClass opClass()     const { return _opClass; }
269};
270
271
272// forward declaration
273class StaticInstPtr;
274
275/**
276 * Generic yet ISA-dependent static instruction class.
277 *
278 * This class builds on StaticInstBase, defining fields and interfaces
279 * that are generic across all ISAs but that differ in details
280 * according to the specific ISA being used.
281 */
282class StaticInst : public StaticInstBase
283{
284  public:
285    /// Binary extended machine instruction type.
286    typedef TheISA::ExtMachInst ExtMachInst;
287    /// Logical register index type.
288    typedef TheISA::RegIndex RegIndex;
289
290    enum {
291        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
292        MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
293    };
294
295
296    /// Return logical index (architectural reg num) of i'th destination reg.
297    /// Only the entries from 0 through numDestRegs()-1 are valid.
298    RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
299
300    /// Return logical index (architectural reg num) of i'th source reg.
301    /// Only the entries from 0 through numSrcRegs()-1 are valid.
302    RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
303
304    /// Pointer to a statically allocated "null" instruction object.
305    /// Used to give eaCompInst() and memAccInst() something to return
306    /// when called on non-memory instructions.
307    static StaticInstPtr nullStaticInstPtr;
308
309    /**
310     * Memory references only: returns "fake" instruction representing
311     * the effective address part of the memory operation.  Used to
312     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
313     * just the EA computation.
314     */
315    virtual const
316    StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
317
318    /**
319     * Memory references only: returns "fake" instruction representing
320     * the memory access part of the memory operation.  Used to
321     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
322     * just the memory access (not the EA computation).
323     */
324    virtual const
325    StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
326
327    /// The binary machine instruction.
328    const ExtMachInst machInst;
329
330  protected:
331
332    /// See destRegIdx().
333    RegIndex _destRegIdx[MaxInstDestRegs];
334    /// See srcRegIdx().
335    RegIndex _srcRegIdx[MaxInstSrcRegs];
336
337    /**
338     * Base mnemonic (e.g., "add").  Used by generateDisassembly()
339     * methods.  Also useful to readily identify instructions from
340     * within the debugger when #cachedDisassembly has not been
341     * initialized.
342     */
343    const char *mnemonic;
344
345    /**
346     * String representation of disassembly (lazily evaluated via
347     * disassemble()).
348     */
349    mutable std::string *cachedDisassembly;
350
351    /**
352     * Internal function to generate disassembly string.
353     */
354    virtual std::string
355    generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
356
357    /// Constructor.
358    StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
359        : StaticInstBase(__opClass),
360          machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
361    { }
362
363  public:
364    virtual ~StaticInst();
365
366/**
367 * The execute() signatures are auto-generated by scons based on the
368 * set of CPU models we are compiling in today.
369 */
370#include "cpu/static_inst_exec_sigs.hh"
371
372    virtual void advancePC(TheISA::PCState &pcState) const = 0;
373
374    /**
375     * Return the microop that goes with a particular micropc. This should
376     * only be defined/used in macroops which will contain microops
377     */
378    virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
379
380    /**
381     * Return the target address for a PC-relative branch.
382     * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
383     * should be true).
384     */
385    virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
386
387    /**
388     * Return the target address for an indirect branch (jump).  The
389     * register value is read from the supplied thread context, so
390     * the result is valid only if the thread context is about to
391     * execute the branch in question.  Invalid if not an indirect
392     * branch (i.e. isIndirectCtrl() should be true).
393     */
394    virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
395
396    /**
397     * Return true if the instruction is a control transfer, and if so,
398     * return the target address as well.
399     */
400    bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
401                         TheISA::PCState &tgt) const;
402
403    /**
404     * Return string representation of disassembled instruction.
405     * The default version of this function will call the internal
406     * virtual generateDisassembly() function to get the string,
407     * then cache it in #cachedDisassembly.  If the disassembly
408     * should not be cached, this function should be overridden directly.
409     */
410    virtual const std::string &disassemble(Addr pc,
411        const SymbolTable *symtab = 0) const;
412
413    /// Return name of machine instruction
414    std::string getName() { return mnemonic; }
415};
416
417typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
418
419/// Reference-counted pointer to a StaticInst object.
420/// This type should be used instead of "StaticInst *" so that
421/// StaticInst objects can be properly reference-counted.
422class StaticInstPtr : public RefCountingPtr<StaticInst>
423{
424  public:
425    /// Constructor.
426    StaticInstPtr()
427        : RefCountingPtr<StaticInst>()
428    {
429    }
430
431    /// Conversion from "StaticInst *".
432    StaticInstPtr(StaticInst *p)
433        : RefCountingPtr<StaticInst>(p)
434    {
435    }
436
437    /// Copy constructor.
438    StaticInstPtr(const StaticInstPtr &r)
439        : RefCountingPtr<StaticInst>(r)
440    {
441    }
442
443    /// Convert to pointer to StaticInstBase class.
444    operator const StaticInstBasePtr()
445    {
446        return this->get();
447    }
448};
449
450#endif // __CPU_STATIC_INST_HH__
451