static_inst.hh revision 7784
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#ifndef __CPU_STATIC_INST_HH__ 32#define __CPU_STATIC_INST_HH__ 33 34#include <bitset> 35#include <string> 36 37#include "arch/isa_traits.hh" 38#include "arch/types.hh" 39#include "arch/registers.hh" 40#include "config/the_isa.hh" 41#include "base/hashmap.hh" 42#include "base/misc.hh" 43#include "base/refcnt.hh" 44#include "base/types.hh" 45#include "cpu/op_class.hh" 46#include "sim/fault.hh" 47 48// forward declarations 49struct AlphaSimpleImpl; 50struct OzoneImpl; 51struct SimpleImpl; 52class ThreadContext; 53class DynInst; 54class Packet; 55 56class O3CPUImpl; 57template <class Impl> class BaseO3DynInst; 58typedef BaseO3DynInst<O3CPUImpl> O3DynInst; 59template <class Impl> class OzoneDynInst; 60class InOrderDynInst; 61 62class CheckerCPU; 63class FastCPU; 64class AtomicSimpleCPU; 65class TimingSimpleCPU; 66class InorderCPU; 67class SymbolTable; 68class AddrDecodePage; 69 70namespace Trace { 71 class InstRecord; 72} 73 74/** 75 * Base, ISA-independent static instruction class. 76 * 77 * The main component of this class is the vector of flags and the 78 * associated methods for reading them. Any object that can rely 79 * solely on these flags can process instructions without being 80 * recompiled for multiple ISAs. 81 */ 82class StaticInstBase : public RefCounted 83{ 84 public: 85 86 /// Set of boolean static instruction properties. 87 /// 88 /// Notes: 89 /// - The IsInteger and IsFloating flags are based on the class of 90 /// registers accessed by the instruction. Although most 91 /// instructions will have exactly one of these two flags set, it 92 /// is possible for an instruction to have neither (e.g., direct 93 /// unconditional branches, memory barriers) or both (e.g., an 94 /// FP/int conversion). 95 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore 96 /// will be set. 97 /// - If IsControl is set, then exactly one of IsDirectControl or 98 /// IsIndirect Control will be set, and exactly one of 99 /// IsCondControl or IsUncondControl will be set. 100 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are 101 /// implemented as flags since in the current model there's no 102 /// other way for instructions to inject behavior into the 103 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU 104 /// model we should be able to get rid of these flags and 105 /// implement this behavior via the execute() methods. 106 /// 107 enum Flags { 108 IsNop, ///< Is a no-op (no effect at all). 109 110 IsInteger, ///< References integer regs. 111 IsFloating, ///< References FP regs. 112 113 IsMemRef, ///< References memory (load, store, or prefetch). 114 IsLoad, ///< Reads from memory (load or prefetch). 115 IsStore, ///< Writes to memory. 116 IsStoreConditional, ///< Store conditional instruction. 117 IsIndexed, ///< Accesses memory with an indexed address computation 118 IsInstPrefetch, ///< Instruction-cache prefetch. 119 IsDataPrefetch, ///< Data-cache prefetch. 120 IsCopy, ///< Fast Cache block copy 121 122 IsControl, ///< Control transfer instruction. 123 IsDirectControl, ///< PC relative control transfer. 124 IsIndirectControl, ///< Register indirect control transfer. 125 IsCondControl, ///< Conditional control transfer. 126 IsUncondControl, ///< Unconditional control transfer. 127 IsCall, ///< Subroutine call. 128 IsReturn, ///< Subroutine return. 129 130 IsCondDelaySlot,///< Conditional Delay-Slot Instruction 131 132 IsThreadSync, ///< Thread synchronization operation. 133 134 IsSerializing, ///< Serializes pipeline: won't execute until all 135 /// older instructions have committed. 136 IsSerializeBefore, 137 IsSerializeAfter, 138 IsMemBarrier, ///< Is a memory barrier 139 IsWriteBarrier, ///< Is a write barrier 140 IsReadBarrier, ///< Is a read barrier 141 IsERET, /// <- Causes the IFU to stall (MIPS ISA) 142 143 IsNonSpeculative, ///< Should not be executed speculatively 144 IsQuiesce, ///< Is a quiesce instruction 145 146 IsIprAccess, ///< Accesses IPRs 147 IsUnverifiable, ///< Can't be verified by a checker 148 149 IsSyscall, ///< Causes a system call to be emulated in syscall 150 /// emulation mode. 151 152 //Flags for microcode 153 IsMacroop, ///< Is a macroop containing microops 154 IsMicroop, ///< Is a microop 155 IsDelayedCommit, ///< This microop doesn't commit right away 156 IsLastMicroop, ///< This microop ends a microop sequence 157 IsFirstMicroop, ///< This microop begins a microop sequence 158 //This flag doesn't do anything yet 159 IsMicroBranch, ///< This microop branches within the microcode for a macroop 160 IsDspOp, 161 IsSquashAfter, ///< Squash all uncommitted state after executed 162 NumFlags 163 }; 164 165 protected: 166 167 /// Flag values for this instruction. 168 std::bitset<NumFlags> flags; 169 170 /// See opClass(). 171 OpClass _opClass; 172 173 /// See numSrcRegs(). 174 int8_t _numSrcRegs; 175 176 /// See numDestRegs(). 177 int8_t _numDestRegs; 178 179 /// The following are used to track physical register usage 180 /// for machines with separate int & FP reg files. 181 //@{ 182 int8_t _numFPDestRegs; 183 int8_t _numIntDestRegs; 184 //@} 185 186 /// Constructor. 187 /// It's important to initialize everything here to a sane 188 /// default, since the decoder generally only overrides 189 /// the fields that are meaningful for the particular 190 /// instruction. 191 StaticInstBase(OpClass __opClass) 192 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 193 _numFPDestRegs(0), _numIntDestRegs(0) 194 { 195 } 196 197 public: 198 199 /// @name Register information. 200 /// The sum of numFPDestRegs() and numIntDestRegs() equals 201 /// numDestRegs(). The former two functions are used to track 202 /// physical register usage for machines with separate int & FP 203 /// reg files. 204 //@{ 205 /// Number of source registers. 206 int8_t numSrcRegs() const { return _numSrcRegs; } 207 /// Number of destination registers. 208 int8_t numDestRegs() const { return _numDestRegs; } 209 /// Number of floating-point destination regs. 210 int8_t numFPDestRegs() const { return _numFPDestRegs; } 211 /// Number of integer destination regs. 212 int8_t numIntDestRegs() const { return _numIntDestRegs; } 213 //@} 214 215 /// @name Flag accessors. 216 /// These functions are used to access the values of the various 217 /// instruction property flags. See StaticInstBase::Flags for descriptions 218 /// of the individual flags. 219 //@{ 220 221 bool isNop() const { return flags[IsNop]; } 222 223 bool isMemRef() const { return flags[IsMemRef]; } 224 bool isLoad() const { return flags[IsLoad]; } 225 bool isStore() const { return flags[IsStore]; } 226 bool isStoreConditional() const { return flags[IsStoreConditional]; } 227 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 228 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 229 bool isPrefetch() const { return isInstPrefetch() || 230 isDataPrefetch(); } 231 bool isCopy() const { return flags[IsCopy];} 232 233 bool isInteger() const { return flags[IsInteger]; } 234 bool isFloating() const { return flags[IsFloating]; } 235 236 bool isControl() const { return flags[IsControl]; } 237 bool isCall() const { return flags[IsCall]; } 238 bool isReturn() const { return flags[IsReturn]; } 239 bool isDirectCtrl() const { return flags[IsDirectControl]; } 240 bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 241 bool isCondCtrl() const { return flags[IsCondControl]; } 242 bool isUncondCtrl() const { return flags[IsUncondControl]; } 243 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; } 244 245 bool isThreadSync() const { return flags[IsThreadSync]; } 246 bool isSerializing() const { return flags[IsSerializing] || 247 flags[IsSerializeBefore] || 248 flags[IsSerializeAfter]; } 249 bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 250 bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 251 bool isSquashAfter() const { return flags[IsSquashAfter]; } 252 bool isMemBarrier() const { return flags[IsMemBarrier]; } 253 bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 254 bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 255 bool isQuiesce() const { return flags[IsQuiesce]; } 256 bool isIprAccess() const { return flags[IsIprAccess]; } 257 bool isUnverifiable() const { return flags[IsUnverifiable]; } 258 bool isSyscall() const { return flags[IsSyscall]; } 259 bool isMacroop() const { return flags[IsMacroop]; } 260 bool isMicroop() const { return flags[IsMicroop]; } 261 bool isDelayedCommit() const { return flags[IsDelayedCommit]; } 262 bool isLastMicroop() const { return flags[IsLastMicroop]; } 263 bool isFirstMicroop() const { return flags[IsFirstMicroop]; } 264 //This flag doesn't do anything yet 265 bool isMicroBranch() const { return flags[IsMicroBranch]; } 266 //@} 267 268 void setLastMicroop() { flags[IsLastMicroop] = true; } 269 void setDelayedCommit() { flags[IsDelayedCommit] = true; } 270 271 /// Operation class. Used to select appropriate function unit in issue. 272 OpClass opClass() const { return _opClass; } 273}; 274 275 276// forward declaration 277class StaticInstPtr; 278 279/** 280 * Generic yet ISA-dependent static instruction class. 281 * 282 * This class builds on StaticInstBase, defining fields and interfaces 283 * that are generic across all ISAs but that differ in details 284 * according to the specific ISA being used. 285 */ 286class StaticInst : public StaticInstBase 287{ 288 public: 289 290 /// Binary machine instruction type. 291 typedef TheISA::MachInst MachInst; 292 /// Binary extended machine instruction type. 293 typedef TheISA::ExtMachInst ExtMachInst; 294 /// Logical register index type. 295 typedef TheISA::RegIndex RegIndex; 296 297 enum { 298 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 299 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs 300 }; 301 302 303 /// Return logical index (architectural reg num) of i'th destination reg. 304 /// Only the entries from 0 through numDestRegs()-1 are valid. 305 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; } 306 307 /// Return logical index (architectural reg num) of i'th source reg. 308 /// Only the entries from 0 through numSrcRegs()-1 are valid. 309 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; } 310 311 /// Pointer to a statically allocated "null" instruction object. 312 /// Used to give eaCompInst() and memAccInst() something to return 313 /// when called on non-memory instructions. 314 static StaticInstPtr nullStaticInstPtr; 315 316 /** 317 * Memory references only: returns "fake" instruction representing 318 * the effective address part of the memory operation. Used to 319 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 320 * just the EA computation. 321 */ 322 virtual const 323 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; } 324 325 /** 326 * Memory references only: returns "fake" instruction representing 327 * the memory access part of the memory operation. Used to 328 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 329 * just the memory access (not the EA computation). 330 */ 331 virtual const 332 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; } 333 334 /// The binary machine instruction. 335 const ExtMachInst machInst; 336 337 protected: 338 339 /// See destRegIdx(). 340 RegIndex _destRegIdx[MaxInstDestRegs]; 341 /// See srcRegIdx(). 342 RegIndex _srcRegIdx[MaxInstSrcRegs]; 343 344 /** 345 * Base mnemonic (e.g., "add"). Used by generateDisassembly() 346 * methods. Also useful to readily identify instructions from 347 * within the debugger when #cachedDisassembly has not been 348 * initialized. 349 */ 350 const char *mnemonic; 351 352 /** 353 * String representation of disassembly (lazily evaluated via 354 * disassemble()). 355 */ 356 mutable std::string *cachedDisassembly; 357 358 /** 359 * Internal function to generate disassembly string. 360 */ 361 virtual std::string 362 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 363 364 /// Constructor. 365 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) 366 : StaticInstBase(__opClass), 367 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) 368 { } 369 370 public: 371 virtual ~StaticInst(); 372 373/** 374 * The execute() signatures are auto-generated by scons based on the 375 * set of CPU models we are compiling in today. 376 */ 377#include "cpu/static_inst_exec_sigs.hh" 378 379 virtual void advancePC(TheISA::PCState &pcState) const = 0; 380 381 /** 382 * Return the microop that goes with a particular micropc. This should 383 * only be defined/used in macroops which will contain microops 384 */ 385 virtual StaticInstPtr fetchMicroop(MicroPC upc) const; 386 387 /** 388 * Return the target address for a PC-relative branch. 389 * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 390 * should be true). 391 */ 392 virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const; 393 394 /** 395 * Return the target address for an indirect branch (jump). The 396 * register value is read from the supplied thread context, so 397 * the result is valid only if the thread context is about to 398 * execute the branch in question. Invalid if not an indirect 399 * branch (i.e. isIndirectCtrl() should be true). 400 */ 401 virtual TheISA::PCState branchTarget(ThreadContext *tc) const; 402 403 /** 404 * Return true if the instruction is a control transfer, and if so, 405 * return the target address as well. 406 */ 407 bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, 408 TheISA::PCState &tgt) const; 409 410 /** 411 * Return string representation of disassembled instruction. 412 * The default version of this function will call the internal 413 * virtual generateDisassembly() function to get the string, 414 * then cache it in #cachedDisassembly. If the disassembly 415 * should not be cached, this function should be overridden directly. 416 */ 417 virtual const std::string &disassemble(Addr pc, 418 const SymbolTable *symtab = 0) const; 419 420 /// Decoded instruction cache type. 421 /// For now we're using a generic hash_map; this seems to work 422 /// pretty well. 423 typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache; 424 425 /// A cache of decoded instruction objects. 426 static DecodeCache decodeCache; 427 428 /** 429 * Dump some basic stats on the decode cache hash map. 430 * Only gets called if DECODE_CACHE_HASH_STATS is defined. 431 */ 432 static void dumpDecodeCacheStats(); 433 434 /// Decode a machine instruction. 435 /// @param mach_inst The binary instruction to decode. 436 /// @retval A pointer to the corresponding StaticInst object. 437 //This is defined as inlined below. 438 static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr); 439 440 /// Return name of machine instruction 441 std::string getName() { return mnemonic; } 442 443 /// Decoded instruction cache type, for address decoding. 444 /// A generic hash_map is used. 445 typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache; 446 447 /// A cache of decoded instruction objects from addresses. 448 static AddrDecodeCache addrDecodeCache; 449 450 struct cacheElement 451 { 452 Addr page_addr; 453 AddrDecodePage *decodePage; 454 455 cacheElement() : decodePage(NULL) { } 456 }; 457 458 /// An array of recently decoded instructions. 459 // might not use an array if there is only two elements 460 static struct cacheElement recentDecodes[2]; 461 462 /// Updates the recently decoded instructions entries 463 /// @param page_addr The page address recently used. 464 /// @param decodePage Pointer to decoding page containing the decoded 465 /// instruction. 466 static inline void 467 updateCache(Addr page_addr, AddrDecodePage *decodePage) 468 { 469 recentDecodes[1].page_addr = recentDecodes[0].page_addr; 470 recentDecodes[1].decodePage = recentDecodes[0].decodePage; 471 recentDecodes[0].page_addr = page_addr; 472 recentDecodes[0].decodePage = decodePage; 473 } 474 475 /// Searches the decoded instruction cache for instruction decoding. 476 /// If it is not found, then we decode the instruction. 477 /// Otherwise, we get the instruction from the cache and move it into 478 /// the address-to-instruction decoding page. 479 /// @param mach_inst The binary instruction to decode. 480 /// @param addr The address that contained the binary instruction. 481 /// @param decodePage Pointer to decoding page containing the instruction. 482 /// @retval A pointer to the corresponding StaticInst object. 483 //This is defined as inlined below. 484 static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr, 485 AddrDecodePage *decodePage); 486}; 487 488typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr; 489 490/// Reference-counted pointer to a StaticInst object. 491/// This type should be used instead of "StaticInst *" so that 492/// StaticInst objects can be properly reference-counted. 493class StaticInstPtr : public RefCountingPtr<StaticInst> 494{ 495 public: 496 /// Constructor. 497 StaticInstPtr() 498 : RefCountingPtr<StaticInst>() 499 { 500 } 501 502 /// Conversion from "StaticInst *". 503 StaticInstPtr(StaticInst *p) 504 : RefCountingPtr<StaticInst>(p) 505 { 506 } 507 508 /// Copy constructor. 509 StaticInstPtr(const StaticInstPtr &r) 510 : RefCountingPtr<StaticInst>(r) 511 { 512 } 513 514 /// Construct directly from machine instruction. 515 /// Calls StaticInst::decode(). 516 explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr) 517 : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr)) 518 { 519 } 520 521 /// Convert to pointer to StaticInstBase class. 522 operator const StaticInstBasePtr() 523 { 524 return this->get(); 525 } 526}; 527 528/// A page of a list of decoded instructions from an address. 529class AddrDecodePage 530{ 531 typedef TheISA::ExtMachInst ExtMachInst; 532 protected: 533 StaticInstPtr instructions[TheISA::PageBytes]; 534 bool valid[TheISA::PageBytes]; 535 Addr lowerMask; 536 537 public: 538 /// Constructor 539 AddrDecodePage() 540 { 541 lowerMask = TheISA::PageBytes - 1; 542 memset(valid, 0, TheISA::PageBytes); 543 } 544 545 /// Checks if the instruction is already decoded and the machine 546 /// instruction in the cache matches the current machine instruction 547 /// related to the address 548 /// @param mach_inst The binary instruction to check 549 /// @param addr The address containing the instruction 550 bool 551 decoded(ExtMachInst mach_inst, Addr addr) 552 { 553 return (valid[addr & lowerMask] && 554 (instructions[addr & lowerMask]->machInst == mach_inst)); 555 } 556 557 /// Returns the instruction object. decoded should be called first 558 /// to check if the instruction is valid. 559 /// @param addr The address of the instruction. 560 /// @retval A pointer to the corresponding StaticInst object. 561 StaticInstPtr 562 getInst(Addr addr) 563 { 564 return instructions[addr & lowerMask]; 565 } 566 567 /// Inserts a pointer to a StaticInst object into the list of decoded 568 /// instructions on the page. 569 /// @param addr The address of the instruction. 570 /// @param si A pointer to the corresponding StaticInst object. 571 void 572 insert(Addr addr, StaticInstPtr &si) 573 { 574 instructions[addr & lowerMask] = si; 575 valid[addr & lowerMask] = true; 576 } 577}; 578 579 580inline StaticInstPtr 581StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr) 582{ 583#ifdef DECODE_CACHE_HASH_STATS 584 // Simple stats on decode hash_map. Turns out the default 585 // hash function is as good as anything I could come up with. 586 const int dump_every_n = 10000000; 587 static int decodes_til_dump = dump_every_n; 588 589 if (--decodes_til_dump == 0) { 590 dumpDecodeCacheStats(); 591 decodes_til_dump = dump_every_n; 592 } 593#endif 594 595 Addr page_addr = addr & ~(TheISA::PageBytes - 1); 596 597 // checks recently decoded addresses 598 if (recentDecodes[0].decodePage && 599 page_addr == recentDecodes[0].page_addr) { 600 if (recentDecodes[0].decodePage->decoded(mach_inst, addr)) 601 return recentDecodes[0].decodePage->getInst(addr); 602 603 return searchCache(mach_inst, addr, recentDecodes[0].decodePage); 604 } 605 606 if (recentDecodes[1].decodePage && 607 page_addr == recentDecodes[1].page_addr) { 608 if (recentDecodes[1].decodePage->decoded(mach_inst, addr)) 609 return recentDecodes[1].decodePage->getInst(addr); 610 611 return searchCache(mach_inst, addr, recentDecodes[1].decodePage); 612 } 613 614 // searches the page containing the address to decode 615 AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr); 616 if (iter != addrDecodeCache.end()) { 617 updateCache(page_addr, iter->second); 618 if (iter->second->decoded(mach_inst, addr)) 619 return iter->second->getInst(addr); 620 621 return searchCache(mach_inst, addr, iter->second); 622 } 623 624 // creates a new object for a page of decoded instructions 625 AddrDecodePage *decodePage = new AddrDecodePage; 626 addrDecodeCache[page_addr] = decodePage; 627 updateCache(page_addr, decodePage); 628 return searchCache(mach_inst, addr, decodePage); 629} 630 631inline StaticInstPtr 632StaticInst::searchCache(ExtMachInst mach_inst, Addr addr, 633 AddrDecodePage *decodePage) 634{ 635 DecodeCache::iterator iter = decodeCache.find(mach_inst); 636 if (iter != decodeCache.end()) { 637 decodePage->insert(addr, iter->second); 638 return iter->second; 639 } 640 641 StaticInstPtr si = TheISA::decodeInst(mach_inst); 642 decodePage->insert(addr, si); 643 decodeCache[mach_inst] = si; 644 return si; 645} 646 647#endif // __CPU_STATIC_INST_HH__ 648