static_inst.hh revision 7725:00ea9430643b
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_STATIC_INST_HH__
32#define __CPU_STATIC_INST_HH__
33
34#include <bitset>
35#include <string>
36
37#include "arch/isa_traits.hh"
38#include "arch/types.hh"
39#include "arch/registers.hh"
40#include "config/the_isa.hh"
41#include "base/hashmap.hh"
42#include "base/misc.hh"
43#include "base/refcnt.hh"
44#include "base/types.hh"
45#include "cpu/op_class.hh"
46#include "sim/fault.hh"
47
48// forward declarations
49struct AlphaSimpleImpl;
50struct OzoneImpl;
51struct SimpleImpl;
52class ThreadContext;
53class DynInst;
54class Packet;
55
56class O3CPUImpl;
57template <class Impl> class BaseO3DynInst;
58typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
59template <class Impl> class OzoneDynInst;
60class InOrderDynInst;
61
62class CheckerCPU;
63class FastCPU;
64class AtomicSimpleCPU;
65class TimingSimpleCPU;
66class InorderCPU;
67class SymbolTable;
68class AddrDecodePage;
69
70namespace Trace {
71    class InstRecord;
72}
73
74/**
75 * Base, ISA-independent static instruction class.
76 *
77 * The main component of this class is the vector of flags and the
78 * associated methods for reading them.  Any object that can rely
79 * solely on these flags can process instructions without being
80 * recompiled for multiple ISAs.
81 */
82class StaticInstBase : public RefCounted
83{
84  public:
85
86    /// Set of boolean static instruction properties.
87    ///
88    /// Notes:
89    /// - The IsInteger and IsFloating flags are based on the class of
90    /// registers accessed by the instruction.  Although most
91    /// instructions will have exactly one of these two flags set, it
92    /// is possible for an instruction to have neither (e.g., direct
93    /// unconditional branches, memory barriers) or both (e.g., an
94    /// FP/int conversion).
95    /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
96    /// will be set.
97    /// - If IsControl is set, then exactly one of IsDirectControl or
98    /// IsIndirect Control will be set, and exactly one of
99    /// IsCondControl or IsUncondControl will be set.
100    /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
101    /// implemented as flags since in the current model there's no
102    /// other way for instructions to inject behavior into the
103    /// pipeline outside of fetch.  Once we go to an exec-in-exec CPU
104    /// model we should be able to get rid of these flags and
105    /// implement this behavior via the execute() methods.
106    ///
107    enum Flags {
108        IsNop,          ///< Is a no-op (no effect at all).
109
110        IsInteger,      ///< References integer regs.
111        IsFloating,     ///< References FP regs.
112
113        IsMemRef,       ///< References memory (load, store, or prefetch).
114        IsLoad,         ///< Reads from memory (load or prefetch).
115        IsStore,        ///< Writes to memory.
116        IsStoreConditional,    ///< Store conditional instruction.
117        IsIndexed,      ///< Accesses memory with an indexed address computation
118        IsInstPrefetch, ///< Instruction-cache prefetch.
119        IsDataPrefetch, ///< Data-cache prefetch.
120        IsCopy,         ///< Fast Cache block copy
121
122        IsControl,              ///< Control transfer instruction.
123        IsDirectControl,        ///< PC relative control transfer.
124        IsIndirectControl,      ///< Register indirect control transfer.
125        IsCondControl,          ///< Conditional control transfer.
126        IsUncondControl,        ///< Unconditional control transfer.
127        IsCall,                 ///< Subroutine call.
128        IsReturn,               ///< Subroutine return.
129
130        IsCondDelaySlot,///< Conditional Delay-Slot Instruction
131
132        IsThreadSync,   ///< Thread synchronization operation.
133
134        IsSerializing,  ///< Serializes pipeline: won't execute until all
135                        /// older instructions have committed.
136        IsSerializeBefore,
137        IsSerializeAfter,
138        IsMemBarrier,   ///< Is a memory barrier
139        IsWriteBarrier, ///< Is a write barrier
140        IsReadBarrier,  ///< Is a read barrier
141        IsERET, /// <- Causes the IFU to stall (MIPS ISA)
142
143        IsNonSpeculative, ///< Should not be executed speculatively
144        IsQuiesce,      ///< Is a quiesce instruction
145
146        IsIprAccess,    ///< Accesses IPRs
147        IsUnverifiable, ///< Can't be verified by a checker
148
149        IsSyscall,      ///< Causes a system call to be emulated in syscall
150                        /// emulation mode.
151
152        //Flags for microcode
153        IsMacroop,      ///< Is a macroop containing microops
154        IsMicroop,      ///< Is a microop
155        IsDelayedCommit,        ///< This microop doesn't commit right away
156        IsLastMicroop,  ///< This microop ends a microop sequence
157        IsFirstMicroop, ///< This microop begins a microop sequence
158        //This flag doesn't do anything yet
159        IsMicroBranch,  ///< This microop branches within the microcode for a macroop
160        IsDspOp,
161
162        NumFlags
163    };
164
165  protected:
166
167    /// Flag values for this instruction.
168    std::bitset<NumFlags> flags;
169
170    /// See opClass().
171    OpClass _opClass;
172
173    /// See numSrcRegs().
174    int8_t _numSrcRegs;
175
176    /// See numDestRegs().
177    int8_t _numDestRegs;
178
179    /// The following are used to track physical register usage
180    /// for machines with separate int & FP reg files.
181    //@{
182    int8_t _numFPDestRegs;
183    int8_t _numIntDestRegs;
184    //@}
185
186    /// Constructor.
187    /// It's important to initialize everything here to a sane
188    /// default, since the decoder generally only overrides
189    /// the fields that are meaningful for the particular
190    /// instruction.
191    StaticInstBase(OpClass __opClass)
192        : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
193          _numFPDestRegs(0), _numIntDestRegs(0)
194    {
195    }
196
197  public:
198
199    /// @name Register information.
200    /// The sum of numFPDestRegs() and numIntDestRegs() equals
201    /// numDestRegs().  The former two functions are used to track
202    /// physical register usage for machines with separate int & FP
203    /// reg files.
204    //@{
205    /// Number of source registers.
206    int8_t numSrcRegs()  const { return _numSrcRegs; }
207    /// Number of destination registers.
208    int8_t numDestRegs() const { return _numDestRegs; }
209    /// Number of floating-point destination regs.
210    int8_t numFPDestRegs()  const { return _numFPDestRegs; }
211    /// Number of integer destination regs.
212    int8_t numIntDestRegs() const { return _numIntDestRegs; }
213    //@}
214
215    /// @name Flag accessors.
216    /// These functions are used to access the values of the various
217    /// instruction property flags.  See StaticInstBase::Flags for descriptions
218    /// of the individual flags.
219    //@{
220
221    bool isNop()          const { return flags[IsNop]; }
222
223    bool isMemRef()       const { return flags[IsMemRef]; }
224    bool isLoad()         const { return flags[IsLoad]; }
225    bool isStore()        const { return flags[IsStore]; }
226    bool isStoreConditional()     const { return flags[IsStoreConditional]; }
227    bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
228    bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
229    bool isPrefetch()     const { return isInstPrefetch() ||
230                                         isDataPrefetch(); }
231    bool isCopy()         const { return flags[IsCopy];}
232
233    bool isInteger()      const { return flags[IsInteger]; }
234    bool isFloating()     const { return flags[IsFloating]; }
235
236    bool isControl()      const { return flags[IsControl]; }
237    bool isCall()         const { return flags[IsCall]; }
238    bool isReturn()       const { return flags[IsReturn]; }
239    bool isDirectCtrl()   const { return flags[IsDirectControl]; }
240    bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
241    bool isCondCtrl()     const { return flags[IsCondControl]; }
242    bool isUncondCtrl()   const { return flags[IsUncondControl]; }
243    bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
244
245    bool isThreadSync()   const { return flags[IsThreadSync]; }
246    bool isSerializing()  const { return flags[IsSerializing] ||
247                                      flags[IsSerializeBefore] ||
248                                      flags[IsSerializeAfter]; }
249    bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
250    bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
251    bool isMemBarrier()   const { return flags[IsMemBarrier]; }
252    bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
253    bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
254    bool isQuiesce() const { return flags[IsQuiesce]; }
255    bool isIprAccess() const { return flags[IsIprAccess]; }
256    bool isUnverifiable() const { return flags[IsUnverifiable]; }
257    bool isSyscall() const { return flags[IsSyscall]; }
258    bool isMacroop() const { return flags[IsMacroop]; }
259    bool isMicroop() const { return flags[IsMicroop]; }
260    bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
261    bool isLastMicroop() const { return flags[IsLastMicroop]; }
262    bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
263    //This flag doesn't do anything yet
264    bool isMicroBranch() const { return flags[IsMicroBranch]; }
265    //@}
266
267    void setLastMicroop() { flags[IsLastMicroop] = true; }
268    void setDelayedCommit() { flags[IsDelayedCommit] = true; }
269
270    /// Operation class.  Used to select appropriate function unit in issue.
271    OpClass opClass()     const { return _opClass; }
272};
273
274
275// forward declaration
276class StaticInstPtr;
277
278/**
279 * Generic yet ISA-dependent static instruction class.
280 *
281 * This class builds on StaticInstBase, defining fields and interfaces
282 * that are generic across all ISAs but that differ in details
283 * according to the specific ISA being used.
284 */
285class StaticInst : public StaticInstBase
286{
287  public:
288
289    /// Binary machine instruction type.
290    typedef TheISA::MachInst MachInst;
291    /// Binary extended machine instruction type.
292    typedef TheISA::ExtMachInst ExtMachInst;
293    /// Logical register index type.
294    typedef TheISA::RegIndex RegIndex;
295
296    enum {
297        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
298        MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
299    };
300
301
302    /// Return logical index (architectural reg num) of i'th destination reg.
303    /// Only the entries from 0 through numDestRegs()-1 are valid.
304    RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
305
306    /// Return logical index (architectural reg num) of i'th source reg.
307    /// Only the entries from 0 through numSrcRegs()-1 are valid.
308    RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
309
310    /// Pointer to a statically allocated "null" instruction object.
311    /// Used to give eaCompInst() and memAccInst() something to return
312    /// when called on non-memory instructions.
313    static StaticInstPtr nullStaticInstPtr;
314
315    /**
316     * Memory references only: returns "fake" instruction representing
317     * the effective address part of the memory operation.  Used to
318     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
319     * just the EA computation.
320     */
321    virtual const
322    StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
323
324    /**
325     * Memory references only: returns "fake" instruction representing
326     * the memory access part of the memory operation.  Used to
327     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
328     * just the memory access (not the EA computation).
329     */
330    virtual const
331    StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
332
333    /// The binary machine instruction.
334    const ExtMachInst machInst;
335
336  protected:
337
338    /// See destRegIdx().
339    RegIndex _destRegIdx[MaxInstDestRegs];
340    /// See srcRegIdx().
341    RegIndex _srcRegIdx[MaxInstSrcRegs];
342
343    /**
344     * Base mnemonic (e.g., "add").  Used by generateDisassembly()
345     * methods.  Also useful to readily identify instructions from
346     * within the debugger when #cachedDisassembly has not been
347     * initialized.
348     */
349    const char *mnemonic;
350
351    /**
352     * String representation of disassembly (lazily evaluated via
353     * disassemble()).
354     */
355    mutable std::string *cachedDisassembly;
356
357    /**
358     * Internal function to generate disassembly string.
359     */
360    virtual std::string
361    generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
362
363    /// Constructor.
364    StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
365        : StaticInstBase(__opClass),
366          machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
367    { }
368
369  public:
370    virtual ~StaticInst();
371
372/**
373 * The execute() signatures are auto-generated by scons based on the
374 * set of CPU models we are compiling in today.
375 */
376#include "cpu/static_inst_exec_sigs.hh"
377
378    virtual void advancePC(TheISA::PCState &pcState) const = 0;
379
380    /**
381     * Return the microop that goes with a particular micropc. This should
382     * only be defined/used in macroops which will contain microops
383     */
384    virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
385
386    /**
387     * Return the target address for a PC-relative branch.
388     * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
389     * should be true).
390     */
391    virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
392
393    /**
394     * Return the target address for an indirect branch (jump).  The
395     * register value is read from the supplied thread context, so
396     * the result is valid only if the thread context is about to
397     * execute the branch in question.  Invalid if not an indirect
398     * branch (i.e. isIndirectCtrl() should be true).
399     */
400    virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
401
402    /**
403     * Return true if the instruction is a control transfer, and if so,
404     * return the target address as well.
405     */
406    bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
407                         TheISA::PCState &tgt) const;
408
409    /**
410     * Return string representation of disassembled instruction.
411     * The default version of this function will call the internal
412     * virtual generateDisassembly() function to get the string,
413     * then cache it in #cachedDisassembly.  If the disassembly
414     * should not be cached, this function should be overridden directly.
415     */
416    virtual const std::string &disassemble(Addr pc,
417        const SymbolTable *symtab = 0) const;
418
419    /// Decoded instruction cache type.
420    /// For now we're using a generic hash_map; this seems to work
421    /// pretty well.
422    typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
423
424    /// A cache of decoded instruction objects.
425    static DecodeCache decodeCache;
426
427    /**
428     * Dump some basic stats on the decode cache hash map.
429     * Only gets called if DECODE_CACHE_HASH_STATS is defined.
430     */
431    static void dumpDecodeCacheStats();
432
433    /// Decode a machine instruction.
434    /// @param mach_inst The binary instruction to decode.
435    /// @retval A pointer to the corresponding StaticInst object.
436    //This is defined as inlined below.
437    static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
438
439    /// Return name of machine instruction
440    std::string getName() { return mnemonic; }
441
442    /// Decoded instruction cache type, for address decoding.
443    /// A generic hash_map is used.
444    typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache;
445
446    /// A cache of decoded instruction objects from addresses.
447    static AddrDecodeCache addrDecodeCache;
448
449    struct cacheElement
450    {
451        Addr page_addr;
452        AddrDecodePage *decodePage;
453
454        cacheElement() : decodePage(NULL) { }
455    };
456
457    /// An array of recently decoded instructions.
458    // might not use an array if there is only two elements
459    static struct cacheElement recentDecodes[2];
460
461    /// Updates the recently decoded instructions entries
462    /// @param page_addr The page address recently used.
463    /// @param decodePage Pointer to decoding page containing the decoded
464    ///                   instruction.
465    static inline void
466    updateCache(Addr page_addr, AddrDecodePage *decodePage)
467    {
468        recentDecodes[1].page_addr = recentDecodes[0].page_addr;
469        recentDecodes[1].decodePage = recentDecodes[0].decodePage;
470        recentDecodes[0].page_addr = page_addr;
471        recentDecodes[0].decodePage = decodePage;
472    }
473
474    /// Searches the decoded instruction cache for instruction decoding.
475    /// If it is not found, then we decode the instruction.
476    /// Otherwise, we get the instruction from the cache and move it into
477    /// the address-to-instruction decoding page.
478    /// @param mach_inst The binary instruction to decode.
479    /// @param addr The address that contained the binary instruction.
480    /// @param decodePage Pointer to decoding page containing the instruction.
481    /// @retval A pointer to the corresponding StaticInst object.
482    //This is defined as inlined below.
483    static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr,
484                                     AddrDecodePage *decodePage);
485};
486
487typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
488
489/// Reference-counted pointer to a StaticInst object.
490/// This type should be used instead of "StaticInst *" so that
491/// StaticInst objects can be properly reference-counted.
492class StaticInstPtr : public RefCountingPtr<StaticInst>
493{
494  public:
495    /// Constructor.
496    StaticInstPtr()
497        : RefCountingPtr<StaticInst>()
498    {
499    }
500
501    /// Conversion from "StaticInst *".
502    StaticInstPtr(StaticInst *p)
503        : RefCountingPtr<StaticInst>(p)
504    {
505    }
506
507    /// Copy constructor.
508    StaticInstPtr(const StaticInstPtr &r)
509        : RefCountingPtr<StaticInst>(r)
510    {
511    }
512
513    /// Construct directly from machine instruction.
514    /// Calls StaticInst::decode().
515    explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr)
516        : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr))
517    {
518    }
519
520    /// Convert to pointer to StaticInstBase class.
521    operator const StaticInstBasePtr()
522    {
523        return this->get();
524    }
525};
526
527/// A page of a list of decoded instructions from an address.
528class AddrDecodePage
529{
530  typedef TheISA::ExtMachInst ExtMachInst;
531  protected:
532    StaticInstPtr instructions[TheISA::PageBytes];
533    bool valid[TheISA::PageBytes];
534    Addr lowerMask;
535
536  public:
537    /// Constructor
538    AddrDecodePage()
539    {
540        lowerMask = TheISA::PageBytes - 1;
541        memset(valid, 0, TheISA::PageBytes);
542    }
543
544    /// Checks if the instruction is already decoded and the machine
545    /// instruction in the cache matches the current machine instruction
546    /// related to the address
547    /// @param mach_inst The binary instruction to check
548    /// @param addr The address containing the instruction
549    bool
550    decoded(ExtMachInst mach_inst, Addr addr)
551    {
552        return (valid[addr & lowerMask] &&
553                (instructions[addr & lowerMask]->machInst == mach_inst));
554    }
555
556    /// Returns the instruction object. decoded should be called first
557    /// to check if the instruction is valid.
558    /// @param addr The address of the instruction.
559    /// @retval A pointer to the corresponding StaticInst object.
560    StaticInstPtr
561    getInst(Addr addr)
562    {
563        return instructions[addr & lowerMask];
564    }
565
566    /// Inserts a pointer to a StaticInst object into the list of decoded
567    /// instructions on the page.
568    /// @param addr The address of the instruction.
569    /// @param si A pointer to the corresponding StaticInst object.
570    void
571    insert(Addr addr, StaticInstPtr &si)
572    {
573        instructions[addr & lowerMask] = si;
574        valid[addr & lowerMask] = true;
575    }
576};
577
578
579inline StaticInstPtr
580StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr)
581{
582#ifdef DECODE_CACHE_HASH_STATS
583    // Simple stats on decode hash_map.  Turns out the default
584    // hash function is as good as anything I could come up with.
585    const int dump_every_n = 10000000;
586    static int decodes_til_dump = dump_every_n;
587
588    if (--decodes_til_dump == 0) {
589        dumpDecodeCacheStats();
590        decodes_til_dump = dump_every_n;
591    }
592#endif
593
594    Addr page_addr = addr & ~(TheISA::PageBytes - 1);
595
596    // checks recently decoded addresses
597    if (recentDecodes[0].decodePage &&
598        page_addr == recentDecodes[0].page_addr) {
599        if (recentDecodes[0].decodePage->decoded(mach_inst, addr))
600            return recentDecodes[0].decodePage->getInst(addr);
601
602        return searchCache(mach_inst, addr, recentDecodes[0].decodePage);
603    }
604
605    if (recentDecodes[1].decodePage &&
606        page_addr == recentDecodes[1].page_addr) {
607        if (recentDecodes[1].decodePage->decoded(mach_inst, addr))
608            return recentDecodes[1].decodePage->getInst(addr);
609
610        return searchCache(mach_inst, addr, recentDecodes[1].decodePage);
611    }
612
613    // searches the page containing the address to decode
614    AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr);
615    if (iter != addrDecodeCache.end()) {
616        updateCache(page_addr, iter->second);
617        if (iter->second->decoded(mach_inst, addr))
618            return iter->second->getInst(addr);
619
620        return searchCache(mach_inst, addr, iter->second);
621    }
622
623    // creates a new object for a page of decoded instructions
624    AddrDecodePage *decodePage = new AddrDecodePage;
625    addrDecodeCache[page_addr] = decodePage;
626    updateCache(page_addr, decodePage);
627    return searchCache(mach_inst, addr, decodePage);
628}
629
630inline StaticInstPtr
631StaticInst::searchCache(ExtMachInst mach_inst, Addr addr,
632                        AddrDecodePage *decodePage)
633{
634    DecodeCache::iterator iter = decodeCache.find(mach_inst);
635    if (iter != decodeCache.end()) {
636        decodePage->insert(addr, iter->second);
637        return iter->second;
638    }
639
640    StaticInstPtr si = TheISA::decodeInst(mach_inst);
641    decodePage->insert(addr, si);
642    decodeCache[mach_inst] = si;
643    return si;
644}
645
646#endif // __CPU_STATIC_INST_HH__
647