static_inst.hh revision 7680
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#ifndef __CPU_STATIC_INST_HH__ 32#define __CPU_STATIC_INST_HH__ 33 34#include <bitset> 35#include <string> 36 37#include "arch/isa_traits.hh" 38#include "arch/registers.hh" 39#include "config/the_isa.hh" 40#include "base/hashmap.hh" 41#include "base/misc.hh" 42#include "base/refcnt.hh" 43#include "base/types.hh" 44#include "cpu/op_class.hh" 45#include "sim/fault.hh" 46 47// forward declarations 48struct AlphaSimpleImpl; 49struct OzoneImpl; 50struct SimpleImpl; 51class ThreadContext; 52class DynInst; 53class Packet; 54 55class O3CPUImpl; 56template <class Impl> class BaseO3DynInst; 57typedef BaseO3DynInst<O3CPUImpl> O3DynInst; 58template <class Impl> class OzoneDynInst; 59class InOrderDynInst; 60 61class CheckerCPU; 62class FastCPU; 63class AtomicSimpleCPU; 64class TimingSimpleCPU; 65class InorderCPU; 66class SymbolTable; 67class AddrDecodePage; 68 69namespace Trace { 70 class InstRecord; 71} 72 73typedef uint16_t MicroPC; 74 75static const MicroPC MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1); 76 77static inline MicroPC 78romMicroPC(MicroPC upc) 79{ 80 return upc | MicroPCRomBit; 81} 82 83static inline MicroPC 84normalMicroPC(MicroPC upc) 85{ 86 return upc & ~MicroPCRomBit; 87} 88 89static inline bool 90isRomMicroPC(MicroPC upc) 91{ 92 return MicroPCRomBit & upc; 93} 94 95/** 96 * Base, ISA-independent static instruction class. 97 * 98 * The main component of this class is the vector of flags and the 99 * associated methods for reading them. Any object that can rely 100 * solely on these flags can process instructions without being 101 * recompiled for multiple ISAs. 102 */ 103class StaticInstBase : public RefCounted 104{ 105 public: 106 107 /// Set of boolean static instruction properties. 108 /// 109 /// Notes: 110 /// - The IsInteger and IsFloating flags are based on the class of 111 /// registers accessed by the instruction. Although most 112 /// instructions will have exactly one of these two flags set, it 113 /// is possible for an instruction to have neither (e.g., direct 114 /// unconditional branches, memory barriers) or both (e.g., an 115 /// FP/int conversion). 116 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore 117 /// will be set. 118 /// - If IsControl is set, then exactly one of IsDirectControl or 119 /// IsIndirect Control will be set, and exactly one of 120 /// IsCondControl or IsUncondControl will be set. 121 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are 122 /// implemented as flags since in the current model there's no 123 /// other way for instructions to inject behavior into the 124 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU 125 /// model we should be able to get rid of these flags and 126 /// implement this behavior via the execute() methods. 127 /// 128 enum Flags { 129 IsNop, ///< Is a no-op (no effect at all). 130 131 IsInteger, ///< References integer regs. 132 IsFloating, ///< References FP regs. 133 134 IsMemRef, ///< References memory (load, store, or prefetch). 135 IsLoad, ///< Reads from memory (load or prefetch). 136 IsStore, ///< Writes to memory. 137 IsStoreConditional, ///< Store conditional instruction. 138 IsIndexed, ///< Accesses memory with an indexed address computation 139 IsInstPrefetch, ///< Instruction-cache prefetch. 140 IsDataPrefetch, ///< Data-cache prefetch. 141 IsCopy, ///< Fast Cache block copy 142 143 IsControl, ///< Control transfer instruction. 144 IsDirectControl, ///< PC relative control transfer. 145 IsIndirectControl, ///< Register indirect control transfer. 146 IsCondControl, ///< Conditional control transfer. 147 IsUncondControl, ///< Unconditional control transfer. 148 IsCall, ///< Subroutine call. 149 IsReturn, ///< Subroutine return. 150 151 IsCondDelaySlot,///< Conditional Delay-Slot Instruction 152 153 IsThreadSync, ///< Thread synchronization operation. 154 155 IsSerializing, ///< Serializes pipeline: won't execute until all 156 /// older instructions have committed. 157 IsSerializeBefore, 158 IsSerializeAfter, 159 IsMemBarrier, ///< Is a memory barrier 160 IsWriteBarrier, ///< Is a write barrier 161 IsReadBarrier, ///< Is a read barrier 162 IsERET, /// <- Causes the IFU to stall (MIPS ISA) 163 164 IsNonSpeculative, ///< Should not be executed speculatively 165 IsQuiesce, ///< Is a quiesce instruction 166 167 IsIprAccess, ///< Accesses IPRs 168 IsUnverifiable, ///< Can't be verified by a checker 169 170 IsSyscall, ///< Causes a system call to be emulated in syscall 171 /// emulation mode. 172 173 //Flags for microcode 174 IsMacroop, ///< Is a macroop containing microops 175 IsMicroop, ///< Is a microop 176 IsDelayedCommit, ///< This microop doesn't commit right away 177 IsLastMicroop, ///< This microop ends a microop sequence 178 IsFirstMicroop, ///< This microop begins a microop sequence 179 //This flag doesn't do anything yet 180 IsMicroBranch, ///< This microop branches within the microcode for a macroop 181 IsDspOp, 182 183 NumFlags 184 }; 185 186 protected: 187 188 /// Flag values for this instruction. 189 std::bitset<NumFlags> flags; 190 191 /// See opClass(). 192 OpClass _opClass; 193 194 /// See numSrcRegs(). 195 int8_t _numSrcRegs; 196 197 /// See numDestRegs(). 198 int8_t _numDestRegs; 199 200 /// The following are used to track physical register usage 201 /// for machines with separate int & FP reg files. 202 //@{ 203 int8_t _numFPDestRegs; 204 int8_t _numIntDestRegs; 205 //@} 206 207 /// Constructor. 208 /// It's important to initialize everything here to a sane 209 /// default, since the decoder generally only overrides 210 /// the fields that are meaningful for the particular 211 /// instruction. 212 StaticInstBase(OpClass __opClass) 213 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 214 _numFPDestRegs(0), _numIntDestRegs(0) 215 { 216 } 217 218 public: 219 220 /// @name Register information. 221 /// The sum of numFPDestRegs() and numIntDestRegs() equals 222 /// numDestRegs(). The former two functions are used to track 223 /// physical register usage for machines with separate int & FP 224 /// reg files. 225 //@{ 226 /// Number of source registers. 227 int8_t numSrcRegs() const { return _numSrcRegs; } 228 /// Number of destination registers. 229 int8_t numDestRegs() const { return _numDestRegs; } 230 /// Number of floating-point destination regs. 231 int8_t numFPDestRegs() const { return _numFPDestRegs; } 232 /// Number of integer destination regs. 233 int8_t numIntDestRegs() const { return _numIntDestRegs; } 234 //@} 235 236 /// @name Flag accessors. 237 /// These functions are used to access the values of the various 238 /// instruction property flags. See StaticInstBase::Flags for descriptions 239 /// of the individual flags. 240 //@{ 241 242 bool isNop() const { return flags[IsNop]; } 243 244 bool isMemRef() const { return flags[IsMemRef]; } 245 bool isLoad() const { return flags[IsLoad]; } 246 bool isStore() const { return flags[IsStore]; } 247 bool isStoreConditional() const { return flags[IsStoreConditional]; } 248 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 249 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 250 bool isCopy() const { return flags[IsCopy];} 251 252 bool isInteger() const { return flags[IsInteger]; } 253 bool isFloating() const { return flags[IsFloating]; } 254 255 bool isControl() const { return flags[IsControl]; } 256 bool isCall() const { return flags[IsCall]; } 257 bool isReturn() const { return flags[IsReturn]; } 258 bool isDirectCtrl() const { return flags[IsDirectControl]; } 259 bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 260 bool isCondCtrl() const { return flags[IsCondControl]; } 261 bool isUncondCtrl() const { return flags[IsUncondControl]; } 262 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; } 263 264 bool isThreadSync() const { return flags[IsThreadSync]; } 265 bool isSerializing() const { return flags[IsSerializing] || 266 flags[IsSerializeBefore] || 267 flags[IsSerializeAfter]; } 268 bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 269 bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 270 bool isMemBarrier() const { return flags[IsMemBarrier]; } 271 bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 272 bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 273 bool isQuiesce() const { return flags[IsQuiesce]; } 274 bool isIprAccess() const { return flags[IsIprAccess]; } 275 bool isUnverifiable() const { return flags[IsUnverifiable]; } 276 bool isSyscall() const { return flags[IsSyscall]; } 277 bool isMacroop() const { return flags[IsMacroop]; } 278 bool isMicroop() const { return flags[IsMicroop]; } 279 bool isDelayedCommit() const { return flags[IsDelayedCommit]; } 280 bool isLastMicroop() const { return flags[IsLastMicroop]; } 281 bool isFirstMicroop() const { return flags[IsFirstMicroop]; } 282 //This flag doesn't do anything yet 283 bool isMicroBranch() const { return flags[IsMicroBranch]; } 284 //@} 285 286 void setLastMicroop() { flags[IsLastMicroop] = true; } 287 /// Operation class. Used to select appropriate function unit in issue. 288 OpClass opClass() const { return _opClass; } 289}; 290 291 292// forward declaration 293class StaticInstPtr; 294 295/** 296 * Generic yet ISA-dependent static instruction class. 297 * 298 * This class builds on StaticInstBase, defining fields and interfaces 299 * that are generic across all ISAs but that differ in details 300 * according to the specific ISA being used. 301 */ 302class StaticInst : public StaticInstBase 303{ 304 public: 305 306 /// Binary machine instruction type. 307 typedef TheISA::MachInst MachInst; 308 /// Binary extended machine instruction type. 309 typedef TheISA::ExtMachInst ExtMachInst; 310 /// Logical register index type. 311 typedef TheISA::RegIndex RegIndex; 312 313 enum { 314 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 315 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs 316 }; 317 318 319 /// Return logical index (architectural reg num) of i'th destination reg. 320 /// Only the entries from 0 through numDestRegs()-1 are valid. 321 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; } 322 323 /// Return logical index (architectural reg num) of i'th source reg. 324 /// Only the entries from 0 through numSrcRegs()-1 are valid. 325 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; } 326 327 /// Pointer to a statically allocated "null" instruction object. 328 /// Used to give eaCompInst() and memAccInst() something to return 329 /// when called on non-memory instructions. 330 static StaticInstPtr nullStaticInstPtr; 331 332 /** 333 * Memory references only: returns "fake" instruction representing 334 * the effective address part of the memory operation. Used to 335 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 336 * just the EA computation. 337 */ 338 virtual const 339 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; } 340 341 /** 342 * Memory references only: returns "fake" instruction representing 343 * the memory access part of the memory operation. Used to 344 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 345 * just the memory access (not the EA computation). 346 */ 347 virtual const 348 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; } 349 350 /// The binary machine instruction. 351 const ExtMachInst machInst; 352 353 protected: 354 355 /// See destRegIdx(). 356 RegIndex _destRegIdx[MaxInstDestRegs]; 357 /// See srcRegIdx(). 358 RegIndex _srcRegIdx[MaxInstSrcRegs]; 359 360 /** 361 * Base mnemonic (e.g., "add"). Used by generateDisassembly() 362 * methods. Also useful to readily identify instructions from 363 * within the debugger when #cachedDisassembly has not been 364 * initialized. 365 */ 366 const char *mnemonic; 367 368 /** 369 * String representation of disassembly (lazily evaluated via 370 * disassemble()). 371 */ 372 mutable std::string *cachedDisassembly; 373 374 /** 375 * Internal function to generate disassembly string. 376 */ 377 virtual std::string 378 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 379 380 /// Constructor. 381 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) 382 : StaticInstBase(__opClass), 383 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) 384 { } 385 386 public: 387 virtual ~StaticInst(); 388 389/** 390 * The execute() signatures are auto-generated by scons based on the 391 * set of CPU models we are compiling in today. 392 */ 393#include "cpu/static_inst_exec_sigs.hh" 394 395 /** 396 * Return the microop that goes with a particular micropc. This should 397 * only be defined/used in macroops which will contain microops 398 */ 399 virtual StaticInstPtr fetchMicroop(MicroPC micropc); 400 401 /** 402 * Return the target address for a PC-relative branch. 403 * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 404 * should be true). 405 */ 406 virtual Addr branchTarget(Addr branchPC) const; 407 408 /** 409 * Return the target address for an indirect branch (jump). The 410 * register value is read from the supplied thread context, so 411 * the result is valid only if the thread context is about to 412 * execute the branch in question. Invalid if not an indirect 413 * branch (i.e. isIndirectCtrl() should be true). 414 */ 415 virtual Addr branchTarget(ThreadContext *tc) const; 416 417 /** 418 * Return true if the instruction is a control transfer, and if so, 419 * return the target address as well. 420 */ 421 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const; 422 423 /** 424 * Return string representation of disassembled instruction. 425 * The default version of this function will call the internal 426 * virtual generateDisassembly() function to get the string, 427 * then cache it in #cachedDisassembly. If the disassembly 428 * should not be cached, this function should be overridden directly. 429 */ 430 virtual const std::string &disassemble(Addr pc, 431 const SymbolTable *symtab = 0) const; 432 433 /// Decoded instruction cache type. 434 /// For now we're using a generic hash_map; this seems to work 435 /// pretty well. 436 typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache; 437 438 /// A cache of decoded instruction objects. 439 static DecodeCache decodeCache; 440 441 /** 442 * Dump some basic stats on the decode cache hash map. 443 * Only gets called if DECODE_CACHE_HASH_STATS is defined. 444 */ 445 static void dumpDecodeCacheStats(); 446 447 /// Decode a machine instruction. 448 /// @param mach_inst The binary instruction to decode. 449 /// @retval A pointer to the corresponding StaticInst object. 450 //This is defined as inlined below. 451 static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr); 452 453 /// Return name of machine instruction 454 std::string getName() { return mnemonic; } 455 456 /// Decoded instruction cache type, for address decoding. 457 /// A generic hash_map is used. 458 typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache; 459 460 /// A cache of decoded instruction objects from addresses. 461 static AddrDecodeCache addrDecodeCache; 462 463 struct cacheElement 464 { 465 Addr page_addr; 466 AddrDecodePage *decodePage; 467 468 cacheElement() : decodePage(NULL) { } 469 }; 470 471 /// An array of recently decoded instructions. 472 // might not use an array if there is only two elements 473 static struct cacheElement recentDecodes[2]; 474 475 /// Updates the recently decoded instructions entries 476 /// @param page_addr The page address recently used. 477 /// @param decodePage Pointer to decoding page containing the decoded 478 /// instruction. 479 static inline void 480 updateCache(Addr page_addr, AddrDecodePage *decodePage) 481 { 482 recentDecodes[1].page_addr = recentDecodes[0].page_addr; 483 recentDecodes[1].decodePage = recentDecodes[0].decodePage; 484 recentDecodes[0].page_addr = page_addr; 485 recentDecodes[0].decodePage = decodePage; 486 } 487 488 /// Searches the decoded instruction cache for instruction decoding. 489 /// If it is not found, then we decode the instruction. 490 /// Otherwise, we get the instruction from the cache and move it into 491 /// the address-to-instruction decoding page. 492 /// @param mach_inst The binary instruction to decode. 493 /// @param addr The address that contained the binary instruction. 494 /// @param decodePage Pointer to decoding page containing the instruction. 495 /// @retval A pointer to the corresponding StaticInst object. 496 //This is defined as inlined below. 497 static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr, 498 AddrDecodePage *decodePage); 499}; 500 501typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr; 502 503/// Reference-counted pointer to a StaticInst object. 504/// This type should be used instead of "StaticInst *" so that 505/// StaticInst objects can be properly reference-counted. 506class StaticInstPtr : public RefCountingPtr<StaticInst> 507{ 508 public: 509 /// Constructor. 510 StaticInstPtr() 511 : RefCountingPtr<StaticInst>() 512 { 513 } 514 515 /// Conversion from "StaticInst *". 516 StaticInstPtr(StaticInst *p) 517 : RefCountingPtr<StaticInst>(p) 518 { 519 } 520 521 /// Copy constructor. 522 StaticInstPtr(const StaticInstPtr &r) 523 : RefCountingPtr<StaticInst>(r) 524 { 525 } 526 527 /// Construct directly from machine instruction. 528 /// Calls StaticInst::decode(). 529 explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr) 530 : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr)) 531 { 532 } 533 534 /// Convert to pointer to StaticInstBase class. 535 operator const StaticInstBasePtr() 536 { 537 return this->get(); 538 } 539}; 540 541/// A page of a list of decoded instructions from an address. 542class AddrDecodePage 543{ 544 typedef TheISA::ExtMachInst ExtMachInst; 545 protected: 546 StaticInstPtr instructions[TheISA::PageBytes]; 547 bool valid[TheISA::PageBytes]; 548 Addr lowerMask; 549 550 public: 551 /// Constructor 552 AddrDecodePage() 553 { 554 lowerMask = TheISA::PageBytes - 1; 555 memset(valid, 0, TheISA::PageBytes); 556 } 557 558 /// Checks if the instruction is already decoded and the machine 559 /// instruction in the cache matches the current machine instruction 560 /// related to the address 561 /// @param mach_inst The binary instruction to check 562 /// @param addr The address containing the instruction 563 bool 564 decoded(ExtMachInst mach_inst, Addr addr) 565 { 566 return (valid[addr & lowerMask] && 567 (instructions[addr & lowerMask]->machInst == mach_inst)); 568 } 569 570 /// Returns the instruction object. decoded should be called first 571 /// to check if the instruction is valid. 572 /// @param addr The address of the instruction. 573 /// @retval A pointer to the corresponding StaticInst object. 574 StaticInstPtr 575 getInst(Addr addr) 576 { 577 return instructions[addr & lowerMask]; 578 } 579 580 /// Inserts a pointer to a StaticInst object into the list of decoded 581 /// instructions on the page. 582 /// @param addr The address of the instruction. 583 /// @param si A pointer to the corresponding StaticInst object. 584 void 585 insert(Addr addr, StaticInstPtr &si) 586 { 587 instructions[addr & lowerMask] = si; 588 valid[addr & lowerMask] = true; 589 } 590}; 591 592 593inline StaticInstPtr 594StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr) 595{ 596#ifdef DECODE_CACHE_HASH_STATS 597 // Simple stats on decode hash_map. Turns out the default 598 // hash function is as good as anything I could come up with. 599 const int dump_every_n = 10000000; 600 static int decodes_til_dump = dump_every_n; 601 602 if (--decodes_til_dump == 0) { 603 dumpDecodeCacheStats(); 604 decodes_til_dump = dump_every_n; 605 } 606#endif 607 608 Addr page_addr = addr & ~(TheISA::PageBytes - 1); 609 610 // checks recently decoded addresses 611 if (recentDecodes[0].decodePage && 612 page_addr == recentDecodes[0].page_addr) { 613 if (recentDecodes[0].decodePage->decoded(mach_inst, addr)) 614 return recentDecodes[0].decodePage->getInst(addr); 615 616 return searchCache(mach_inst, addr, recentDecodes[0].decodePage); 617 } 618 619 if (recentDecodes[1].decodePage && 620 page_addr == recentDecodes[1].page_addr) { 621 if (recentDecodes[1].decodePage->decoded(mach_inst, addr)) 622 return recentDecodes[1].decodePage->getInst(addr); 623 624 return searchCache(mach_inst, addr, recentDecodes[1].decodePage); 625 } 626 627 // searches the page containing the address to decode 628 AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr); 629 if (iter != addrDecodeCache.end()) { 630 updateCache(page_addr, iter->second); 631 if (iter->second->decoded(mach_inst, addr)) 632 return iter->second->getInst(addr); 633 634 return searchCache(mach_inst, addr, iter->second); 635 } 636 637 // creates a new object for a page of decoded instructions 638 AddrDecodePage *decodePage = new AddrDecodePage; 639 addrDecodeCache[page_addr] = decodePage; 640 updateCache(page_addr, decodePage); 641 return searchCache(mach_inst, addr, decodePage); 642} 643 644inline StaticInstPtr 645StaticInst::searchCache(ExtMachInst mach_inst, Addr addr, 646 AddrDecodePage *decodePage) 647{ 648 DecodeCache::iterator iter = decodeCache.find(mach_inst); 649 if (iter != decodeCache.end()) { 650 decodePage->insert(addr, iter->second); 651 return iter->second; 652 } 653 654 StaticInstPtr si = TheISA::decodeInst(mach_inst); 655 decodePage->insert(addr, si); 656 decodeCache[mach_inst] = si; 657 return si; 658} 659 660#endif // __CPU_STATIC_INST_HH__ 661