static_inst.hh revision 7678
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#ifndef __CPU_STATIC_INST_HH__ 32#define __CPU_STATIC_INST_HH__ 33 34#include <bitset> 35#include <string> 36 37#include "arch/isa_traits.hh" 38#include "arch/utility.hh" 39#include "config/the_isa.hh" 40#include "base/bitfield.hh" 41#include "base/hashmap.hh" 42#include "base/misc.hh" 43#include "base/refcnt.hh" 44#include "base/types.hh" 45#include "cpu/op_class.hh" 46#include "sim/fault.hh" 47 48// forward declarations 49struct AlphaSimpleImpl; 50struct OzoneImpl; 51struct SimpleImpl; 52class ThreadContext; 53class DynInst; 54class Packet; 55 56class O3CPUImpl; 57template <class Impl> class BaseO3DynInst; 58typedef BaseO3DynInst<O3CPUImpl> O3DynInst; 59template <class Impl> class OzoneDynInst; 60class InOrderDynInst; 61 62class CheckerCPU; 63class FastCPU; 64class AtomicSimpleCPU; 65class TimingSimpleCPU; 66class InorderCPU; 67class SymbolTable; 68class AddrDecodePage; 69 70namespace Trace { 71 class InstRecord; 72} 73 74typedef uint16_t MicroPC; 75 76static const MicroPC MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1); 77 78static inline MicroPC 79romMicroPC(MicroPC upc) 80{ 81 return upc | MicroPCRomBit; 82} 83 84static inline MicroPC 85normalMicroPC(MicroPC upc) 86{ 87 return upc & ~MicroPCRomBit; 88} 89 90static inline bool 91isRomMicroPC(MicroPC upc) 92{ 93 return MicroPCRomBit & upc; 94} 95 96/** 97 * Base, ISA-independent static instruction class. 98 * 99 * The main component of this class is the vector of flags and the 100 * associated methods for reading them. Any object that can rely 101 * solely on these flags can process instructions without being 102 * recompiled for multiple ISAs. 103 */ 104class StaticInstBase : public RefCounted 105{ 106 public: 107 108 /// Set of boolean static instruction properties. 109 /// 110 /// Notes: 111 /// - The IsInteger and IsFloating flags are based on the class of 112 /// registers accessed by the instruction. Although most 113 /// instructions will have exactly one of these two flags set, it 114 /// is possible for an instruction to have neither (e.g., direct 115 /// unconditional branches, memory barriers) or both (e.g., an 116 /// FP/int conversion). 117 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore 118 /// will be set. 119 /// - If IsControl is set, then exactly one of IsDirectControl or 120 /// IsIndirect Control will be set, and exactly one of 121 /// IsCondControl or IsUncondControl will be set. 122 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are 123 /// implemented as flags since in the current model there's no 124 /// other way for instructions to inject behavior into the 125 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU 126 /// model we should be able to get rid of these flags and 127 /// implement this behavior via the execute() methods. 128 /// 129 enum Flags { 130 IsNop, ///< Is a no-op (no effect at all). 131 132 IsInteger, ///< References integer regs. 133 IsFloating, ///< References FP regs. 134 135 IsMemRef, ///< References memory (load, store, or prefetch). 136 IsLoad, ///< Reads from memory (load or prefetch). 137 IsStore, ///< Writes to memory. 138 IsStoreConditional, ///< Store conditional instruction. 139 IsIndexed, ///< Accesses memory with an indexed address computation 140 IsInstPrefetch, ///< Instruction-cache prefetch. 141 IsDataPrefetch, ///< Data-cache prefetch. 142 IsCopy, ///< Fast Cache block copy 143 144 IsControl, ///< Control transfer instruction. 145 IsDirectControl, ///< PC relative control transfer. 146 IsIndirectControl, ///< Register indirect control transfer. 147 IsCondControl, ///< Conditional control transfer. 148 IsUncondControl, ///< Unconditional control transfer. 149 IsCall, ///< Subroutine call. 150 IsReturn, ///< Subroutine return. 151 152 IsCondDelaySlot,///< Conditional Delay-Slot Instruction 153 154 IsThreadSync, ///< Thread synchronization operation. 155 156 IsSerializing, ///< Serializes pipeline: won't execute until all 157 /// older instructions have committed. 158 IsSerializeBefore, 159 IsSerializeAfter, 160 IsMemBarrier, ///< Is a memory barrier 161 IsWriteBarrier, ///< Is a write barrier 162 IsReadBarrier, ///< Is a read barrier 163 IsERET, /// <- Causes the IFU to stall (MIPS ISA) 164 165 IsNonSpeculative, ///< Should not be executed speculatively 166 IsQuiesce, ///< Is a quiesce instruction 167 168 IsIprAccess, ///< Accesses IPRs 169 IsUnverifiable, ///< Can't be verified by a checker 170 171 IsSyscall, ///< Causes a system call to be emulated in syscall 172 /// emulation mode. 173 174 //Flags for microcode 175 IsMacroop, ///< Is a macroop containing microops 176 IsMicroop, ///< Is a microop 177 IsDelayedCommit, ///< This microop doesn't commit right away 178 IsLastMicroop, ///< This microop ends a microop sequence 179 IsFirstMicroop, ///< This microop begins a microop sequence 180 //This flag doesn't do anything yet 181 IsMicroBranch, ///< This microop branches within the microcode for a macroop 182 IsDspOp, 183 184 NumFlags 185 }; 186 187 protected: 188 189 /// Flag values for this instruction. 190 std::bitset<NumFlags> flags; 191 192 /// See opClass(). 193 OpClass _opClass; 194 195 /// See numSrcRegs(). 196 int8_t _numSrcRegs; 197 198 /// See numDestRegs(). 199 int8_t _numDestRegs; 200 201 /// The following are used to track physical register usage 202 /// for machines with separate int & FP reg files. 203 //@{ 204 int8_t _numFPDestRegs; 205 int8_t _numIntDestRegs; 206 //@} 207 208 /// Constructor. 209 /// It's important to initialize everything here to a sane 210 /// default, since the decoder generally only overrides 211 /// the fields that are meaningful for the particular 212 /// instruction. 213 StaticInstBase(OpClass __opClass) 214 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 215 _numFPDestRegs(0), _numIntDestRegs(0) 216 { 217 } 218 219 public: 220 221 /// @name Register information. 222 /// The sum of numFPDestRegs() and numIntDestRegs() equals 223 /// numDestRegs(). The former two functions are used to track 224 /// physical register usage for machines with separate int & FP 225 /// reg files. 226 //@{ 227 /// Number of source registers. 228 int8_t numSrcRegs() const { return _numSrcRegs; } 229 /// Number of destination registers. 230 int8_t numDestRegs() const { return _numDestRegs; } 231 /// Number of floating-point destination regs. 232 int8_t numFPDestRegs() const { return _numFPDestRegs; } 233 /// Number of integer destination regs. 234 int8_t numIntDestRegs() const { return _numIntDestRegs; } 235 //@} 236 237 /// @name Flag accessors. 238 /// These functions are used to access the values of the various 239 /// instruction property flags. See StaticInstBase::Flags for descriptions 240 /// of the individual flags. 241 //@{ 242 243 bool isNop() const { return flags[IsNop]; } 244 245 bool isMemRef() const { return flags[IsMemRef]; } 246 bool isLoad() const { return flags[IsLoad]; } 247 bool isStore() const { return flags[IsStore]; } 248 bool isStoreConditional() const { return flags[IsStoreConditional]; } 249 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 250 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 251 bool isCopy() const { return flags[IsCopy];} 252 253 bool isInteger() const { return flags[IsInteger]; } 254 bool isFloating() const { return flags[IsFloating]; } 255 256 bool isControl() const { return flags[IsControl]; } 257 bool isCall() const { return flags[IsCall]; } 258 bool isReturn() const { return flags[IsReturn]; } 259 bool isDirectCtrl() const { return flags[IsDirectControl]; } 260 bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 261 bool isCondCtrl() const { return flags[IsCondControl]; } 262 bool isUncondCtrl() const { return flags[IsUncondControl]; } 263 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; } 264 265 bool isThreadSync() const { return flags[IsThreadSync]; } 266 bool isSerializing() const { return flags[IsSerializing] || 267 flags[IsSerializeBefore] || 268 flags[IsSerializeAfter]; } 269 bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 270 bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 271 bool isMemBarrier() const { return flags[IsMemBarrier]; } 272 bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 273 bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 274 bool isQuiesce() const { return flags[IsQuiesce]; } 275 bool isIprAccess() const { return flags[IsIprAccess]; } 276 bool isUnverifiable() const { return flags[IsUnverifiable]; } 277 bool isSyscall() const { return flags[IsSyscall]; } 278 bool isMacroop() const { return flags[IsMacroop]; } 279 bool isMicroop() const { return flags[IsMicroop]; } 280 bool isDelayedCommit() const { return flags[IsDelayedCommit]; } 281 bool isLastMicroop() const { return flags[IsLastMicroop]; } 282 bool isFirstMicroop() const { return flags[IsFirstMicroop]; } 283 //This flag doesn't do anything yet 284 bool isMicroBranch() const { return flags[IsMicroBranch]; } 285 //@} 286 287 void setLastMicroop() { flags[IsLastMicroop] = true; } 288 /// Operation class. Used to select appropriate function unit in issue. 289 OpClass opClass() const { return _opClass; } 290}; 291 292 293// forward declaration 294class StaticInstPtr; 295 296/** 297 * Generic yet ISA-dependent static instruction class. 298 * 299 * This class builds on StaticInstBase, defining fields and interfaces 300 * that are generic across all ISAs but that differ in details 301 * according to the specific ISA being used. 302 */ 303class StaticInst : public StaticInstBase 304{ 305 public: 306 307 /// Binary machine instruction type. 308 typedef TheISA::MachInst MachInst; 309 /// Binary extended machine instruction type. 310 typedef TheISA::ExtMachInst ExtMachInst; 311 /// Logical register index type. 312 typedef TheISA::RegIndex RegIndex; 313 314 enum { 315 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 316 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs 317 }; 318 319 320 /// Return logical index (architectural reg num) of i'th destination reg. 321 /// Only the entries from 0 through numDestRegs()-1 are valid. 322 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; } 323 324 /// Return logical index (architectural reg num) of i'th source reg. 325 /// Only the entries from 0 through numSrcRegs()-1 are valid. 326 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; } 327 328 /// Pointer to a statically allocated "null" instruction object. 329 /// Used to give eaCompInst() and memAccInst() something to return 330 /// when called on non-memory instructions. 331 static StaticInstPtr nullStaticInstPtr; 332 333 /** 334 * Memory references only: returns "fake" instruction representing 335 * the effective address part of the memory operation. Used to 336 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 337 * just the EA computation. 338 */ 339 virtual const 340 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; } 341 342 /** 343 * Memory references only: returns "fake" instruction representing 344 * the memory access part of the memory operation. Used to 345 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 346 * just the memory access (not the EA computation). 347 */ 348 virtual const 349 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; } 350 351 /// The binary machine instruction. 352 const ExtMachInst machInst; 353 354 protected: 355 356 /// See destRegIdx(). 357 RegIndex _destRegIdx[MaxInstDestRegs]; 358 /// See srcRegIdx(). 359 RegIndex _srcRegIdx[MaxInstSrcRegs]; 360 361 /** 362 * Base mnemonic (e.g., "add"). Used by generateDisassembly() 363 * methods. Also useful to readily identify instructions from 364 * within the debugger when #cachedDisassembly has not been 365 * initialized. 366 */ 367 const char *mnemonic; 368 369 /** 370 * String representation of disassembly (lazily evaluated via 371 * disassemble()). 372 */ 373 mutable std::string *cachedDisassembly; 374 375 /** 376 * Internal function to generate disassembly string. 377 */ 378 virtual std::string 379 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 380 381 /// Constructor. 382 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) 383 : StaticInstBase(__opClass), 384 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) 385 { } 386 387 public: 388 virtual ~StaticInst(); 389 390/** 391 * The execute() signatures are auto-generated by scons based on the 392 * set of CPU models we are compiling in today. 393 */ 394#include "cpu/static_inst_exec_sigs.hh" 395 396 /** 397 * Return the microop that goes with a particular micropc. This should 398 * only be defined/used in macroops which will contain microops 399 */ 400 virtual StaticInstPtr fetchMicroop(MicroPC micropc); 401 402 /** 403 * Return the target address for a PC-relative branch. 404 * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 405 * should be true). 406 */ 407 virtual Addr branchTarget(Addr branchPC) const; 408 409 /** 410 * Return the target address for an indirect branch (jump). The 411 * register value is read from the supplied thread context, so 412 * the result is valid only if the thread context is about to 413 * execute the branch in question. Invalid if not an indirect 414 * branch (i.e. isIndirectCtrl() should be true). 415 */ 416 virtual Addr branchTarget(ThreadContext *tc) const; 417 418 /** 419 * Return true if the instruction is a control transfer, and if so, 420 * return the target address as well. 421 */ 422 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const; 423 424 /** 425 * Return string representation of disassembled instruction. 426 * The default version of this function will call the internal 427 * virtual generateDisassembly() function to get the string, 428 * then cache it in #cachedDisassembly. If the disassembly 429 * should not be cached, this function should be overridden directly. 430 */ 431 virtual const std::string &disassemble(Addr pc, 432 const SymbolTable *symtab = 0) const; 433 434 /// Decoded instruction cache type. 435 /// For now we're using a generic hash_map; this seems to work 436 /// pretty well. 437 typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache; 438 439 /// A cache of decoded instruction objects. 440 static DecodeCache decodeCache; 441 442 /** 443 * Dump some basic stats on the decode cache hash map. 444 * Only gets called if DECODE_CACHE_HASH_STATS is defined. 445 */ 446 static void dumpDecodeCacheStats(); 447 448 /// Decode a machine instruction. 449 /// @param mach_inst The binary instruction to decode. 450 /// @retval A pointer to the corresponding StaticInst object. 451 //This is defined as inlined below. 452 static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr); 453 454 /// Return name of machine instruction 455 std::string getName() { return mnemonic; } 456 457 /// Decoded instruction cache type, for address decoding. 458 /// A generic hash_map is used. 459 typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache; 460 461 /// A cache of decoded instruction objects from addresses. 462 static AddrDecodeCache addrDecodeCache; 463 464 struct cacheElement 465 { 466 Addr page_addr; 467 AddrDecodePage *decodePage; 468 469 cacheElement() : decodePage(NULL) { } 470 }; 471 472 /// An array of recently decoded instructions. 473 // might not use an array if there is only two elements 474 static struct cacheElement recentDecodes[2]; 475 476 /// Updates the recently decoded instructions entries 477 /// @param page_addr The page address recently used. 478 /// @param decodePage Pointer to decoding page containing the decoded 479 /// instruction. 480 static inline void 481 updateCache(Addr page_addr, AddrDecodePage *decodePage) 482 { 483 recentDecodes[1].page_addr = recentDecodes[0].page_addr; 484 recentDecodes[1].decodePage = recentDecodes[0].decodePage; 485 recentDecodes[0].page_addr = page_addr; 486 recentDecodes[0].decodePage = decodePage; 487 } 488 489 /// Searches the decoded instruction cache for instruction decoding. 490 /// If it is not found, then we decode the instruction. 491 /// Otherwise, we get the instruction from the cache and move it into 492 /// the address-to-instruction decoding page. 493 /// @param mach_inst The binary instruction to decode. 494 /// @param addr The address that contained the binary instruction. 495 /// @param decodePage Pointer to decoding page containing the instruction. 496 /// @retval A pointer to the corresponding StaticInst object. 497 //This is defined as inlined below. 498 static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr, 499 AddrDecodePage *decodePage); 500}; 501 502typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr; 503 504/// Reference-counted pointer to a StaticInst object. 505/// This type should be used instead of "StaticInst *" so that 506/// StaticInst objects can be properly reference-counted. 507class StaticInstPtr : public RefCountingPtr<StaticInst> 508{ 509 public: 510 /// Constructor. 511 StaticInstPtr() 512 : RefCountingPtr<StaticInst>() 513 { 514 } 515 516 /// Conversion from "StaticInst *". 517 StaticInstPtr(StaticInst *p) 518 : RefCountingPtr<StaticInst>(p) 519 { 520 } 521 522 /// Copy constructor. 523 StaticInstPtr(const StaticInstPtr &r) 524 : RefCountingPtr<StaticInst>(r) 525 { 526 } 527 528 /// Construct directly from machine instruction. 529 /// Calls StaticInst::decode(). 530 explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr) 531 : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr)) 532 { 533 } 534 535 /// Convert to pointer to StaticInstBase class. 536 operator const StaticInstBasePtr() 537 { 538 return this->get(); 539 } 540}; 541 542/// A page of a list of decoded instructions from an address. 543class AddrDecodePage 544{ 545 typedef TheISA::ExtMachInst ExtMachInst; 546 protected: 547 StaticInstPtr instructions[TheISA::PageBytes]; 548 bool valid[TheISA::PageBytes]; 549 Addr lowerMask; 550 551 public: 552 /// Constructor 553 AddrDecodePage() 554 { 555 lowerMask = TheISA::PageBytes - 1; 556 memset(valid, 0, TheISA::PageBytes); 557 } 558 559 /// Checks if the instruction is already decoded and the machine 560 /// instruction in the cache matches the current machine instruction 561 /// related to the address 562 /// @param mach_inst The binary instruction to check 563 /// @param addr The address containing the instruction 564 bool 565 decoded(ExtMachInst mach_inst, Addr addr) 566 { 567 return (valid[addr & lowerMask] && 568 (instructions[addr & lowerMask]->machInst == mach_inst)); 569 } 570 571 /// Returns the instruction object. decoded should be called first 572 /// to check if the instruction is valid. 573 /// @param addr The address of the instruction. 574 /// @retval A pointer to the corresponding StaticInst object. 575 StaticInstPtr 576 getInst(Addr addr) 577 { 578 return instructions[addr & lowerMask]; 579 } 580 581 /// Inserts a pointer to a StaticInst object into the list of decoded 582 /// instructions on the page. 583 /// @param addr The address of the instruction. 584 /// @param si A pointer to the corresponding StaticInst object. 585 void 586 insert(Addr addr, StaticInstPtr &si) 587 { 588 instructions[addr & lowerMask] = si; 589 valid[addr & lowerMask] = true; 590 } 591}; 592 593 594inline StaticInstPtr 595StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr) 596{ 597#ifdef DECODE_CACHE_HASH_STATS 598 // Simple stats on decode hash_map. Turns out the default 599 // hash function is as good as anything I could come up with. 600 const int dump_every_n = 10000000; 601 static int decodes_til_dump = dump_every_n; 602 603 if (--decodes_til_dump == 0) { 604 dumpDecodeCacheStats(); 605 decodes_til_dump = dump_every_n; 606 } 607#endif 608 609 Addr page_addr = addr & ~(TheISA::PageBytes - 1); 610 611 // checks recently decoded addresses 612 if (recentDecodes[0].decodePage && 613 page_addr == recentDecodes[0].page_addr) { 614 if (recentDecodes[0].decodePage->decoded(mach_inst, addr)) 615 return recentDecodes[0].decodePage->getInst(addr); 616 617 return searchCache(mach_inst, addr, recentDecodes[0].decodePage); 618 } 619 620 if (recentDecodes[1].decodePage && 621 page_addr == recentDecodes[1].page_addr) { 622 if (recentDecodes[1].decodePage->decoded(mach_inst, addr)) 623 return recentDecodes[1].decodePage->getInst(addr); 624 625 return searchCache(mach_inst, addr, recentDecodes[1].decodePage); 626 } 627 628 // searches the page containing the address to decode 629 AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr); 630 if (iter != addrDecodeCache.end()) { 631 updateCache(page_addr, iter->second); 632 if (iter->second->decoded(mach_inst, addr)) 633 return iter->second->getInst(addr); 634 635 return searchCache(mach_inst, addr, iter->second); 636 } 637 638 // creates a new object for a page of decoded instructions 639 AddrDecodePage *decodePage = new AddrDecodePage; 640 addrDecodeCache[page_addr] = decodePage; 641 updateCache(page_addr, decodePage); 642 return searchCache(mach_inst, addr, decodePage); 643} 644 645inline StaticInstPtr 646StaticInst::searchCache(ExtMachInst mach_inst, Addr addr, 647 AddrDecodePage *decodePage) 648{ 649 DecodeCache::iterator iter = decodeCache.find(mach_inst); 650 if (iter != decodeCache.end()) { 651 decodePage->insert(addr, iter->second); 652 return iter->second; 653 } 654 655 StaticInstPtr si = TheISA::decodeInst(mach_inst); 656 decodePage->insert(addr, si); 657 decodeCache[mach_inst] = si; 658 return si; 659} 660 661#endif // __CPU_STATIC_INST_HH__ 662