static_inst.hh revision 7619:0a32de653c10
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#ifndef __CPU_STATIC_INST_HH__ 32#define __CPU_STATIC_INST_HH__ 33 34#include <bitset> 35#include <string> 36 37#include "arch/isa_traits.hh" 38#include "arch/utility.hh" 39#include "config/the_isa.hh" 40#include "base/bitfield.hh" 41#include "base/hashmap.hh" 42#include "base/misc.hh" 43#include "base/refcnt.hh" 44#include "base/types.hh" 45#include "cpu/op_class.hh" 46#include "sim/faults.hh" 47#include "sim/faults.hh" 48 49// forward declarations 50struct AlphaSimpleImpl; 51struct OzoneImpl; 52struct SimpleImpl; 53class ThreadContext; 54class DynInst; 55class Packet; 56 57class O3CPUImpl; 58template <class Impl> class BaseO3DynInst; 59typedef BaseO3DynInst<O3CPUImpl> O3DynInst; 60template <class Impl> class OzoneDynInst; 61class InOrderDynInst; 62 63class CheckerCPU; 64class FastCPU; 65class AtomicSimpleCPU; 66class TimingSimpleCPU; 67class InorderCPU; 68class SymbolTable; 69class AddrDecodePage; 70 71namespace Trace { 72 class InstRecord; 73} 74 75typedef uint16_t MicroPC; 76 77static const MicroPC MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1); 78 79static inline MicroPC 80romMicroPC(MicroPC upc) 81{ 82 return upc | MicroPCRomBit; 83} 84 85static inline MicroPC 86normalMicroPC(MicroPC upc) 87{ 88 return upc & ~MicroPCRomBit; 89} 90 91static inline bool 92isRomMicroPC(MicroPC upc) 93{ 94 return MicroPCRomBit & upc; 95} 96 97/** 98 * Base, ISA-independent static instruction class. 99 * 100 * The main component of this class is the vector of flags and the 101 * associated methods for reading them. Any object that can rely 102 * solely on these flags can process instructions without being 103 * recompiled for multiple ISAs. 104 */ 105class StaticInstBase : public RefCounted 106{ 107 public: 108 109 /// Set of boolean static instruction properties. 110 /// 111 /// Notes: 112 /// - The IsInteger and IsFloating flags are based on the class of 113 /// registers accessed by the instruction. Although most 114 /// instructions will have exactly one of these two flags set, it 115 /// is possible for an instruction to have neither (e.g., direct 116 /// unconditional branches, memory barriers) or both (e.g., an 117 /// FP/int conversion). 118 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore 119 /// will be set. 120 /// - If IsControl is set, then exactly one of IsDirectControl or 121 /// IsIndirect Control will be set, and exactly one of 122 /// IsCondControl or IsUncondControl will be set. 123 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are 124 /// implemented as flags since in the current model there's no 125 /// other way for instructions to inject behavior into the 126 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU 127 /// model we should be able to get rid of these flags and 128 /// implement this behavior via the execute() methods. 129 /// 130 enum Flags { 131 IsNop, ///< Is a no-op (no effect at all). 132 133 IsInteger, ///< References integer regs. 134 IsFloating, ///< References FP regs. 135 136 IsMemRef, ///< References memory (load, store, or prefetch). 137 IsLoad, ///< Reads from memory (load or prefetch). 138 IsStore, ///< Writes to memory. 139 IsStoreConditional, ///< Store conditional instruction. 140 IsIndexed, ///< Accesses memory with an indexed address computation 141 IsInstPrefetch, ///< Instruction-cache prefetch. 142 IsDataPrefetch, ///< Data-cache prefetch. 143 IsCopy, ///< Fast Cache block copy 144 145 IsControl, ///< Control transfer instruction. 146 IsDirectControl, ///< PC relative control transfer. 147 IsIndirectControl, ///< Register indirect control transfer. 148 IsCondControl, ///< Conditional control transfer. 149 IsUncondControl, ///< Unconditional control transfer. 150 IsCall, ///< Subroutine call. 151 IsReturn, ///< Subroutine return. 152 153 IsCondDelaySlot,///< Conditional Delay-Slot Instruction 154 155 IsThreadSync, ///< Thread synchronization operation. 156 157 IsSerializing, ///< Serializes pipeline: won't execute until all 158 /// older instructions have committed. 159 IsSerializeBefore, 160 IsSerializeAfter, 161 IsMemBarrier, ///< Is a memory barrier 162 IsWriteBarrier, ///< Is a write barrier 163 IsReadBarrier, ///< Is a read barrier 164 IsERET, /// <- Causes the IFU to stall (MIPS ISA) 165 166 IsNonSpeculative, ///< Should not be executed speculatively 167 IsQuiesce, ///< Is a quiesce instruction 168 169 IsIprAccess, ///< Accesses IPRs 170 IsUnverifiable, ///< Can't be verified by a checker 171 172 IsSyscall, ///< Causes a system call to be emulated in syscall 173 /// emulation mode. 174 175 //Flags for microcode 176 IsMacroop, ///< Is a macroop containing microops 177 IsMicroop, ///< Is a microop 178 IsDelayedCommit, ///< This microop doesn't commit right away 179 IsLastMicroop, ///< This microop ends a microop sequence 180 IsFirstMicroop, ///< This microop begins a microop sequence 181 //This flag doesn't do anything yet 182 IsMicroBranch, ///< This microop branches within the microcode for a macroop 183 IsDspOp, 184 185 NumFlags 186 }; 187 188 protected: 189 190 /// Flag values for this instruction. 191 std::bitset<NumFlags> flags; 192 193 /// See opClass(). 194 OpClass _opClass; 195 196 /// See numSrcRegs(). 197 int8_t _numSrcRegs; 198 199 /// See numDestRegs(). 200 int8_t _numDestRegs; 201 202 /// The following are used to track physical register usage 203 /// for machines with separate int & FP reg files. 204 //@{ 205 int8_t _numFPDestRegs; 206 int8_t _numIntDestRegs; 207 //@} 208 209 /// Constructor. 210 /// It's important to initialize everything here to a sane 211 /// default, since the decoder generally only overrides 212 /// the fields that are meaningful for the particular 213 /// instruction. 214 StaticInstBase(OpClass __opClass) 215 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 216 _numFPDestRegs(0), _numIntDestRegs(0) 217 { 218 } 219 220 public: 221 222 /// @name Register information. 223 /// The sum of numFPDestRegs() and numIntDestRegs() equals 224 /// numDestRegs(). The former two functions are used to track 225 /// physical register usage for machines with separate int & FP 226 /// reg files. 227 //@{ 228 /// Number of source registers. 229 int8_t numSrcRegs() const { return _numSrcRegs; } 230 /// Number of destination registers. 231 int8_t numDestRegs() const { return _numDestRegs; } 232 /// Number of floating-point destination regs. 233 int8_t numFPDestRegs() const { return _numFPDestRegs; } 234 /// Number of integer destination regs. 235 int8_t numIntDestRegs() const { return _numIntDestRegs; } 236 //@} 237 238 /// @name Flag accessors. 239 /// These functions are used to access the values of the various 240 /// instruction property flags. See StaticInstBase::Flags for descriptions 241 /// of the individual flags. 242 //@{ 243 244 bool isNop() const { return flags[IsNop]; } 245 246 bool isMemRef() const { return flags[IsMemRef]; } 247 bool isLoad() const { return flags[IsLoad]; } 248 bool isStore() const { return flags[IsStore]; } 249 bool isStoreConditional() const { return flags[IsStoreConditional]; } 250 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 251 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 252 bool isCopy() const { return flags[IsCopy];} 253 254 bool isInteger() const { return flags[IsInteger]; } 255 bool isFloating() const { return flags[IsFloating]; } 256 257 bool isControl() const { return flags[IsControl]; } 258 bool isCall() const { return flags[IsCall]; } 259 bool isReturn() const { return flags[IsReturn]; } 260 bool isDirectCtrl() const { return flags[IsDirectControl]; } 261 bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 262 bool isCondCtrl() const { return flags[IsCondControl]; } 263 bool isUncondCtrl() const { return flags[IsUncondControl]; } 264 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; } 265 266 bool isThreadSync() const { return flags[IsThreadSync]; } 267 bool isSerializing() const { return flags[IsSerializing] || 268 flags[IsSerializeBefore] || 269 flags[IsSerializeAfter]; } 270 bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 271 bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 272 bool isMemBarrier() const { return flags[IsMemBarrier]; } 273 bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 274 bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 275 bool isQuiesce() const { return flags[IsQuiesce]; } 276 bool isIprAccess() const { return flags[IsIprAccess]; } 277 bool isUnverifiable() const { return flags[IsUnverifiable]; } 278 bool isSyscall() const { return flags[IsSyscall]; } 279 bool isMacroop() const { return flags[IsMacroop]; } 280 bool isMicroop() const { return flags[IsMicroop]; } 281 bool isDelayedCommit() const { return flags[IsDelayedCommit]; } 282 bool isLastMicroop() const { return flags[IsLastMicroop]; } 283 bool isFirstMicroop() const { return flags[IsFirstMicroop]; } 284 //This flag doesn't do anything yet 285 bool isMicroBranch() const { return flags[IsMicroBranch]; } 286 //@} 287 288 void setLastMicroop() { flags[IsLastMicroop] = true; } 289 /// Operation class. Used to select appropriate function unit in issue. 290 OpClass opClass() const { return _opClass; } 291}; 292 293 294// forward declaration 295class StaticInstPtr; 296 297/** 298 * Generic yet ISA-dependent static instruction class. 299 * 300 * This class builds on StaticInstBase, defining fields and interfaces 301 * that are generic across all ISAs but that differ in details 302 * according to the specific ISA being used. 303 */ 304class StaticInst : public StaticInstBase 305{ 306 public: 307 308 /// Binary machine instruction type. 309 typedef TheISA::MachInst MachInst; 310 /// Binary extended machine instruction type. 311 typedef TheISA::ExtMachInst ExtMachInst; 312 /// Logical register index type. 313 typedef TheISA::RegIndex RegIndex; 314 315 enum { 316 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 317 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs 318 }; 319 320 321 /// Return logical index (architectural reg num) of i'th destination reg. 322 /// Only the entries from 0 through numDestRegs()-1 are valid. 323 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; } 324 325 /// Return logical index (architectural reg num) of i'th source reg. 326 /// Only the entries from 0 through numSrcRegs()-1 are valid. 327 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; } 328 329 /// Pointer to a statically allocated "null" instruction object. 330 /// Used to give eaCompInst() and memAccInst() something to return 331 /// when called on non-memory instructions. 332 static StaticInstPtr nullStaticInstPtr; 333 334 /** 335 * Memory references only: returns "fake" instruction representing 336 * the effective address part of the memory operation. Used to 337 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 338 * just the EA computation. 339 */ 340 virtual const 341 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; } 342 343 /** 344 * Memory references only: returns "fake" instruction representing 345 * the memory access part of the memory operation. Used to 346 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 347 * just the memory access (not the EA computation). 348 */ 349 virtual const 350 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; } 351 352 /// The binary machine instruction. 353 const ExtMachInst machInst; 354 355 protected: 356 357 /// See destRegIdx(). 358 RegIndex _destRegIdx[MaxInstDestRegs]; 359 /// See srcRegIdx(). 360 RegIndex _srcRegIdx[MaxInstSrcRegs]; 361 362 /** 363 * Base mnemonic (e.g., "add"). Used by generateDisassembly() 364 * methods. Also useful to readily identify instructions from 365 * within the debugger when #cachedDisassembly has not been 366 * initialized. 367 */ 368 const char *mnemonic; 369 370 /** 371 * String representation of disassembly (lazily evaluated via 372 * disassemble()). 373 */ 374 mutable std::string *cachedDisassembly; 375 376 /** 377 * Internal function to generate disassembly string. 378 */ 379 virtual std::string 380 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 381 382 /// Constructor. 383 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) 384 : StaticInstBase(__opClass), 385 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) 386 { } 387 388 public: 389 virtual ~StaticInst(); 390 391/** 392 * The execute() signatures are auto-generated by scons based on the 393 * set of CPU models we are compiling in today. 394 */ 395#include "cpu/static_inst_exec_sigs.hh" 396 397 /** 398 * Return the microop that goes with a particular micropc. This should 399 * only be defined/used in macroops which will contain microops 400 */ 401 virtual StaticInstPtr fetchMicroop(MicroPC micropc); 402 403 /** 404 * Return the target address for a PC-relative branch. 405 * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 406 * should be true). 407 */ 408 virtual Addr branchTarget(Addr branchPC) const; 409 410 /** 411 * Return the target address for an indirect branch (jump). The 412 * register value is read from the supplied thread context, so 413 * the result is valid only if the thread context is about to 414 * execute the branch in question. Invalid if not an indirect 415 * branch (i.e. isIndirectCtrl() should be true). 416 */ 417 virtual Addr branchTarget(ThreadContext *tc) const; 418 419 /** 420 * Return true if the instruction is a control transfer, and if so, 421 * return the target address as well. 422 */ 423 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const; 424 425 /** 426 * Return string representation of disassembled instruction. 427 * The default version of this function will call the internal 428 * virtual generateDisassembly() function to get the string, 429 * then cache it in #cachedDisassembly. If the disassembly 430 * should not be cached, this function should be overridden directly. 431 */ 432 virtual const std::string &disassemble(Addr pc, 433 const SymbolTable *symtab = 0) const; 434 435 /// Decoded instruction cache type. 436 /// For now we're using a generic hash_map; this seems to work 437 /// pretty well. 438 typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache; 439 440 /// A cache of decoded instruction objects. 441 static DecodeCache decodeCache; 442 443 /** 444 * Dump some basic stats on the decode cache hash map. 445 * Only gets called if DECODE_CACHE_HASH_STATS is defined. 446 */ 447 static void dumpDecodeCacheStats(); 448 449 /// Decode a machine instruction. 450 /// @param mach_inst The binary instruction to decode. 451 /// @retval A pointer to the corresponding StaticInst object. 452 //This is defined as inlined below. 453 static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr); 454 455 /// Return name of machine instruction 456 std::string getName() { return mnemonic; } 457 458 /// Decoded instruction cache type, for address decoding. 459 /// A generic hash_map is used. 460 typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache; 461 462 /// A cache of decoded instruction objects from addresses. 463 static AddrDecodeCache addrDecodeCache; 464 465 struct cacheElement 466 { 467 Addr page_addr; 468 AddrDecodePage *decodePage; 469 470 cacheElement() : decodePage(NULL) { } 471 }; 472 473 /// An array of recently decoded instructions. 474 // might not use an array if there is only two elements 475 static struct cacheElement recentDecodes[2]; 476 477 /// Updates the recently decoded instructions entries 478 /// @param page_addr The page address recently used. 479 /// @param decodePage Pointer to decoding page containing the decoded 480 /// instruction. 481 static inline void 482 updateCache(Addr page_addr, AddrDecodePage *decodePage) 483 { 484 recentDecodes[1].page_addr = recentDecodes[0].page_addr; 485 recentDecodes[1].decodePage = recentDecodes[0].decodePage; 486 recentDecodes[0].page_addr = page_addr; 487 recentDecodes[0].decodePage = decodePage; 488 } 489 490 /// Searches the decoded instruction cache for instruction decoding. 491 /// If it is not found, then we decode the instruction. 492 /// Otherwise, we get the instruction from the cache and move it into 493 /// the address-to-instruction decoding page. 494 /// @param mach_inst The binary instruction to decode. 495 /// @param addr The address that contained the binary instruction. 496 /// @param decodePage Pointer to decoding page containing the instruction. 497 /// @retval A pointer to the corresponding StaticInst object. 498 //This is defined as inlined below. 499 static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr, 500 AddrDecodePage *decodePage); 501}; 502 503typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr; 504 505/// Reference-counted pointer to a StaticInst object. 506/// This type should be used instead of "StaticInst *" so that 507/// StaticInst objects can be properly reference-counted. 508class StaticInstPtr : public RefCountingPtr<StaticInst> 509{ 510 public: 511 /// Constructor. 512 StaticInstPtr() 513 : RefCountingPtr<StaticInst>() 514 { 515 } 516 517 /// Conversion from "StaticInst *". 518 StaticInstPtr(StaticInst *p) 519 : RefCountingPtr<StaticInst>(p) 520 { 521 } 522 523 /// Copy constructor. 524 StaticInstPtr(const StaticInstPtr &r) 525 : RefCountingPtr<StaticInst>(r) 526 { 527 } 528 529 /// Construct directly from machine instruction. 530 /// Calls StaticInst::decode(). 531 explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr) 532 : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr)) 533 { 534 } 535 536 /// Convert to pointer to StaticInstBase class. 537 operator const StaticInstBasePtr() 538 { 539 return this->get(); 540 } 541}; 542 543/// A page of a list of decoded instructions from an address. 544class AddrDecodePage 545{ 546 typedef TheISA::ExtMachInst ExtMachInst; 547 protected: 548 StaticInstPtr instructions[TheISA::PageBytes]; 549 bool valid[TheISA::PageBytes]; 550 Addr lowerMask; 551 552 public: 553 /// Constructor 554 AddrDecodePage() 555 { 556 lowerMask = TheISA::PageBytes - 1; 557 memset(valid, 0, TheISA::PageBytes); 558 } 559 560 /// Checks if the instruction is already decoded and the machine 561 /// instruction in the cache matches the current machine instruction 562 /// related to the address 563 /// @param mach_inst The binary instruction to check 564 /// @param addr The address containing the instruction 565 bool 566 decoded(ExtMachInst mach_inst, Addr addr) 567 { 568 return (valid[addr & lowerMask] && 569 (instructions[addr & lowerMask]->machInst == mach_inst)); 570 } 571 572 /// Returns the instruction object. decoded should be called first 573 /// to check if the instruction is valid. 574 /// @param addr The address of the instruction. 575 /// @retval A pointer to the corresponding StaticInst object. 576 StaticInstPtr 577 getInst(Addr addr) 578 { 579 return instructions[addr & lowerMask]; 580 } 581 582 /// Inserts a pointer to a StaticInst object into the list of decoded 583 /// instructions on the page. 584 /// @param addr The address of the instruction. 585 /// @param si A pointer to the corresponding StaticInst object. 586 void 587 insert(Addr addr, StaticInstPtr &si) 588 { 589 instructions[addr & lowerMask] = si; 590 valid[addr & lowerMask] = true; 591 } 592}; 593 594 595inline StaticInstPtr 596StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr) 597{ 598#ifdef DECODE_CACHE_HASH_STATS 599 // Simple stats on decode hash_map. Turns out the default 600 // hash function is as good as anything I could come up with. 601 const int dump_every_n = 10000000; 602 static int decodes_til_dump = dump_every_n; 603 604 if (--decodes_til_dump == 0) { 605 dumpDecodeCacheStats(); 606 decodes_til_dump = dump_every_n; 607 } 608#endif 609 610 Addr page_addr = addr & ~(TheISA::PageBytes - 1); 611 612 // checks recently decoded addresses 613 if (recentDecodes[0].decodePage && 614 page_addr == recentDecodes[0].page_addr) { 615 if (recentDecodes[0].decodePage->decoded(mach_inst, addr)) 616 return recentDecodes[0].decodePage->getInst(addr); 617 618 return searchCache(mach_inst, addr, recentDecodes[0].decodePage); 619 } 620 621 if (recentDecodes[1].decodePage && 622 page_addr == recentDecodes[1].page_addr) { 623 if (recentDecodes[1].decodePage->decoded(mach_inst, addr)) 624 return recentDecodes[1].decodePage->getInst(addr); 625 626 return searchCache(mach_inst, addr, recentDecodes[1].decodePage); 627 } 628 629 // searches the page containing the address to decode 630 AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr); 631 if (iter != addrDecodeCache.end()) { 632 updateCache(page_addr, iter->second); 633 if (iter->second->decoded(mach_inst, addr)) 634 return iter->second->getInst(addr); 635 636 return searchCache(mach_inst, addr, iter->second); 637 } 638 639 // creates a new object for a page of decoded instructions 640 AddrDecodePage *decodePage = new AddrDecodePage; 641 addrDecodeCache[page_addr] = decodePage; 642 updateCache(page_addr, decodePage); 643 return searchCache(mach_inst, addr, decodePage); 644} 645 646inline StaticInstPtr 647StaticInst::searchCache(ExtMachInst mach_inst, Addr addr, 648 AddrDecodePage *decodePage) 649{ 650 DecodeCache::iterator iter = decodeCache.find(mach_inst); 651 if (iter != decodeCache.end()) { 652 decodePage->insert(addr, iter->second); 653 return iter->second; 654 } 655 656 StaticInstPtr si = TheISA::decodeInst(mach_inst); 657 decodePage->insert(addr, si); 658 decodeCache[mach_inst] = si; 659 return si; 660} 661 662#endif // __CPU_STATIC_INST_HH__ 663